Integrated Design Techniques of Physical Unclonable Function and Multi-bit Parallel Exclusive OR Operations

LI Gang; ZHOU Junjie; WANG Pengjun; ZHANG Maolin; GUO Yufeng

doi:10.11999/JEIT240300

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LI Gang, ZHOU Junjie, WANG Pengjun, ZHANG Maolin, GUO Yufeng. Integrated Design Techniques of Physical Unclonable Function and Multi-bit Parallel Exclusive OR Operations[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT240300

Citation:

LI Gang, ZHOU Junjie, WANG Pengjun, ZHANG Maolin, GUO Yufeng. Integrated Design Techniques of Physical Unclonable Function and Multi-bit Parallel Exclusive OR Operations[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT240300

Citation:

LI Gang, ZHOU Junjie, WANG Pengjun, ZHANG Maolin, GUO Yufeng. Integrated Design Techniques of Physical Unclonable Function and Multi-bit Parallel Exclusive OR Operations[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT240300

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Integrated Design Techniques of Physical Unclonable Function and Multi-bit Parallel Exclusive OR Operations

doi: 10.11999/JEIT240300

1.
College of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210003, China
2.
College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou 325035, China

Funds: The National Natural Science Foundation of China (62234008, 62374117), Zhejiang Provincial Natural Science Foundation of China (LY22F040004), China Postdoctoral Science Foundation (2023M731776), Wenzhou Basic Scientific Research Projects (G20240015)

Received Date: 2024-04-19
Rev Recd Date: 2024-08-22

Available Online: 2024-08-30

Abstract

Abstract

Physical Unclonable Functions (PUFs), as well as Exclusive OR (XOR) operations, play an important role in the field of information security. In order to break through the functional barrier between PUF and logic operation, an integrated design scheme of PUF and multi-bit parallel XOR operation circuit based on the random process deviation of Differential Cascode Voltage Switch Logic (DCVSL) XOR gate cascade unit is proposed by studying the working mechanism of PUF and DCVSL. By adding a pre-charge tube at the differential output of the DCVSL XOR gate and setting a control gate at the ground end, three operating modes of the PUF feature information extraction, XOR/ Negated Exclusive OR (XNOR) operation and power control can be switched freely. Meanwhile, for the PUF response stability problem, the unstable bit hybrid screening technique with extreme and golden operating point participation labeling was proposed. Based on TSMC process of 65 nm, a fully customized layout design for a 10-bit input bit-wide circuit with an area of 38.76 μm² was carried out. The experimental results show that the 1024-bit output response can be generated in PUF mode, and a stable key of more than 512 bit can be obtained after hybrid screening, which has good randomness and uniqueness; In the operation mode, 10-bit parallel XOR and XNOR operations can be achieved simultaneously, with power consumption and delay of 2.67 μW and 593.52 ps, respectively. In power control mode, the standby power consumption is only 70.5 nW. The proposed method provides a novel way to break the function-wall of PUF.
- Physical Unclonable Functions (PUF),
- Logical operations,
- Integrated design,
- Stability screening,
- Hardware security

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References(18)

References

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