SMCA: A Framework for Scaling Chiplet-Based Computing-in-Memory Accelerators

LI Wen; WANG Ying; HE Yintao; ZOU Kaiwei; LI Huawei; LI Xiaowei

doi:10.11999/JEIT240284

Volume 46 Issue 11

Nov. 2024

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Article Navigation > Journal of Electronics & Information Technology > 2024 > 46(11): 4081-4091

LI Wen, WANG Ying, HE Yintao, ZOU Kaiwei, LI Huawei, LI Xiaowei. SMCA: A Framework for Scaling Chiplet-Based Computing-in-Memory Accelerators[J]. Journal of Electronics & Information Technology, 2024, 46(11): 4081-4091. doi: 10.11999/JEIT240284

Citation:

LI Wen, WANG Ying, HE Yintao, ZOU Kaiwei, LI Huawei, LI Xiaowei. SMCA: A Framework for Scaling Chiplet-Based Computing-in-Memory Accelerators[J]. Journal of Electronics & Information Technology, 2024, 46(11): 4081-4091. doi: 10.11999/JEIT240284

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SMCA: A Framework for Scaling Chiplet-Based Computing-in-Memory Accelerators

doi: 10.11999/JEIT240284

LI Wen^{1, 2, 3},
WANG Ying^{4, 5
,
,},
HE Yintao^{4, 5},
ZOU Kaiwei⁶,
LI Huawei^{4, 5},
LI Xiaowei^{4, 5}

1.
School of Computer and Information Technology (School of Big Data), Shanxi University Taiyuan 030006, China
2.
Institute of Big Data Science and Industry, Shanxi University Taiyuan 030006, China
3.
Key Laboratory of Computational Intelligence and Chinese Information Processing of Ministry of Education, Shanxi University Taiyuan 030006, China
4.
State Key Laboratory of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
5.
University of Chinese Academy of Sciences, BeiJing 100190, China
6.
Department of Electronic Engineering, Tsinghua University, Beijing 100084, China

Funds: The National Natural Science Foundation of China (62302283), The Basic Research Program of Shanxi Province (Exploration Research)(202303021212015)

Received Date: 2024-04-16
Rev Recd Date: 2024-09-13

Available Online: 2024-09-30

Publish Date: 2024-11-01

Abstract

Abstract

Computing-in-Memory (CiM) architectures based on Resistive Random Access Memory (ReRAM) have been recognized as a promising solution to accelerate deep learning applications. As intelligent applications continue to evolve, deep learning models become larger and larger, which imposes higher demands on the computational and storage resources on processing platforms. However, due to the non-idealism of ReRAM, large-scale ReRAM-based computing systems face severe challenges of low yield and reliability. Chiplet-based architectures assemble multiple small chiplets into a single package, providing higher fabrication yield and lower manufacturing costs, which has become a primary trend in chip design. However, compared to on-chip wiring, the expensive inter-chiplet communication becomes a performance bottleneck for chiplet-based systems which limits the chip’s scalability. As the countermeasure, a novel scaling framework for chiplet-based CiM accelerators, SMCA (SMT-based CiM chiplet Acceleration) is proposed in this paper. This framework comprises an adaptive deep learning task partition strategy and an automated SMT-based workload deployment to generate the most energy-efficient DNN workload scheduling strategy with the minimum data transmission on chiplet-based deep learning accelerators, achieving effective improvement in system performance and efficiency. Experimental results show that compared to existing strategies, the SMCA-generated automatically schedule strategy can reduce the energy costs of inter-chiplet communication by 35%.
- Chiplet,
- Deep learning processor,
- Computing-in-Memory (CiM),
- Task dispatching

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References(24)

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