A Design of On-chip Network with Self-adaptive Reconfigurable Fault–Tolerant Link

XU Dongyu; OUYANG Yiming; HUANG Zhengfeng; LI Jianhua; LIANG Huaguo

doi:10.11999/JEIT240162

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XU Dongyu, OUYANG Yiming, HUANG Zhengfeng, LI Jianhua, LIANG Huaguo. A Design of On-chip Network with Self-adaptive Reconfigurable Fault–Tolerant Link[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT240162

Citation:

XU Dongyu, OUYANG Yiming, HUANG Zhengfeng, LI Jianhua, LIANG Huaguo. A Design of On-chip Network with Self-adaptive Reconfigurable Fault–Tolerant Link[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT240162

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A Design of On-chip Network with Self-adaptive Reconfigurable Fault–Tolerant Link

doi: 10.11999/JEIT240162

1.
School of Computer and Information , Anhui Polytechnic University, Wuhu 241000, China
2.
School of Computer Science and Information Engineering, Hefei University of Technology, Hefei 230009, China
3.
School of Microlectronics, Hefei University of Technology, Hefei 230009, China

Funds: The National Natural Science Foundation of China (62374049, 62174048, 62274052)

Received Date: 2024-03-12
Rev Recd Date: 2024-09-12

Available Online: 2024-09-28

Abstract

Abstract

As chip manufacturing has advanced to the sub-micro-nanometer scale, shrinking technology nodes are accelerating link failures in on-chip network, and the growth of failure links reduces the number of available routing paths and might lead to severe traffic congestion or even system crashes. The difficulty in maintaining the correctness of the on-chip system dramatically rises as the technology node shrinks. Previous schemes typically utilize deflection algorithms to bypass packets. However, they incur additional transmission latency due to hop count and raise the probability of deadlock. In order to achieve normal packet transmission encountering faulty links, a self-adaptive Reconfigurable Fault-tolerant Link NoC design (RFL_NoC) is proposed, which redirects packets encountering a faulty link to another reversible link. The scheme contains a specific implementation of the reversible link and the associated distributed control protocol. The dynamic fault-tolerant link design maximizes the idle, available link and ensures that the network communication is not interrupted in case of link failures. Compared with the advanced fault-tolerant deflection routing algorithm QFCAR-W, RFL_NoC can reduce the average delay by 10%, the area overhead by 14.2%, and the power overhead by 9.3%.
- System-on-Chip (SoC),
- Network-on-Chip (NoC),
- Fault-tolerance,
- Router architecture,
- Routing algorithm

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References(20)

References

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