Wafer-Level Adaptive Testing Method with Low Test Escape

LIANG Huaguo; QU Jinxing; PAN Yuqi; TANG Yuxin; YI Maoxiang; LU Yingchun

doi:10.11999/JEIT230852

Volume 45 Issue 9

Sep. 2023

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Article Navigation > Journal of Electronics & Information Technology > 2023 > 45(9): 3393-3400

LIANG Huaguo, QU Jinxing, PAN Yuqi, TANG Yuxin, YI Maoxiang, LU Yingchun. Wafer-Level Adaptive Testing Method with Low Test Escape[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3393-3400. doi: 10.11999/JEIT230852

Citation:

LIANG Huaguo, QU Jinxing, PAN Yuqi, TANG Yuxin, YI Maoxiang, LU Yingchun. Wafer-Level Adaptive Testing Method with Low Test Escape[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3393-3400. doi: 10.11999/JEIT230852

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Wafer-Level Adaptive Testing Method with Low Test Escape

doi: 10.11999/JEIT230852

School of Microelectronics, Hefei University of Technology, Hefei 230009, China

Funds: The National Major Research Instrument Development Project (62027815), The National Natural Science Foundation of China Key Project (61834006)

Received Date: 2023-08-04
Accepted Date: 2023-08-21
Rev Recd Date: 2023-08-18

Available Online: 2023-08-23

Publish Date: 2023-09-27

Abstract

Abstract

In order to reduce the test cost and improve the test quality in ICs. A wafer-level adaptive test method with low test escapes is proposed. The method reduces the test cost of wafers to be tested by filtering the test set based on the effectiveness of the test item to detect faulty die in historical test data. At the same time, the degree of fluctuation of the parameters in the neighborhood of the die is analyzed, and the parameter differences of the die with fluctuations are amplified and modeled to improve the classification accuracy of the quality prediction model for this type of dies; The dies without fluctuations are used for quality prediction using the valid test set modeling method to reduce the risk of test escapes. Experimental results based on actual wafer production data show that the method can significantly reduce the test item cost of wafers by 40.13% and maintain a low test escape rate of 0.0091%.
- Wafer-level adaptive testing,
- Neighborhood parameter fluctuation,
- Parameter variance,
- Quality prediction

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References(17)

References

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