A RISC-V Test Sequences Generation Method Based on Instruction Generation Constraints

LIU Peng; HU Wenchao; LIU Deqi; HAN Xiaoxia; LIU Yangfan

doi:10.11999/JEIT230480

Volume 45 Issue 9

Sep. 2023

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Article Navigation > Journal of Electronics & Information Technology > 2023 > 45(9): 3141-3149

LIU Peng, HU Wenchao, LIU Deqi, HAN Xiaoxia, LIU Yangfan. A RISC-V Test Sequences Generation Method Based on Instruction Generation Constraints[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3141-3149. doi: 10.11999/JEIT230480

Citation:

LIU Peng, HU Wenchao, LIU Deqi, HAN Xiaoxia, LIU Yangfan. A RISC-V Test Sequences Generation Method Based on Instruction Generation Constraints[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3141-3149. doi: 10.11999/JEIT230480

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A RISC-V Test Sequences Generation Method Based on Instruction Generation Constraints

doi: 10.11999/JEIT230480

1.
College of Information Science & Electronic Engineering, Zhejiang University, Hangzhou 310027, China
2.
HEXIN Technologies Co., Ltd., Guangzhou 510725, China

Received Date: 2023-05-24
Rev Recd Date: 2023-08-23

Available Online: 2023-08-31

Publish Date: 2023-09-27

Abstract

Abstract

In order to avoid the threat of instruction defects to the processor, this paper proposes a RISC-V test sequence generation method based on instruction generation constraints. A test instruction sequence generation framework is constructed based on this method to achieve test instruction generation and instruction defect detection, while addressing the challenges in defining constraints and slow convergence speed in existing test instruction sequence generation methods. Firstly, the instruction generation constraints are defined according to the instruction set architecture specification and instruction verification requirements. These constraints include instruction format constraints, general coverage constraints, and particular coverage constraints, aiming to solve the challenges in defining constraints as the number of instructions increases and improve reusability. Then, a heuristic search strategy is applied to accelerating the convergence rate of coverage by utilizing statistical coverage information. Finally, a solving algorithm is constructed based on the heuristic search strategies to generate test sequences that satisfy the instruction generation constraints. The experimental results show that, compared with the state-of-the-art methods, the convergence time of structural coverage is reduced by 85.62% and numerical coverage is reduced by 57.64%, under the premise of covering all instruction verification requirements. By using this framework to detect open-source processor, instruction defects introduced in the processor decoding and execution stages can be located, providing an efficient method for detecting processor instruction defects.
- Processor,
- RISC-V,
- Instruction defect detection,
- Constrained instruction generation

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References(19)

References

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