Citation: | XU Zhihang, XU Yongye, MA Tongchuan, DU Li, DU Yuan. 3D Contactless Chiplet Interconnects for CMOS Image Sensor[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3150-3156. doi: 10.11999/JEIT230382 |
[1] |
ARAI T, YASUE T, KITAMURA K, et al. A 1.1 μm 33-Mpixel 240-fps 3-D-stacked CMOS image sensor with three-stage cyclic-cyclic-SAR analog-to-digital converters[J]. IEEE Transactions on Electron Devices, 2017, 64(12): 4992–5000. doi: 10.1109/TED.2017.2766297
|
[2] |
CHIU P W, KUNDU S, TANG Qianying, et al. A 65-nm 10-Gb/s 10-mm on-chip serial link featuring a digital-intensive time-based decision feedback equalizer[J]. IEEE Journal of Solid-State Circuits, 2018, 53(4): 1203–1213. doi: 10.1109/JSSC.2017.2774276
|
[3] |
NAVID R, CHEN E H, HOSSAIN M, et al. A 40 Gb/s serial link transceiver in 28 nm CMOS technology[J]. IEEE Journal of Solid-State Circuits, 2015, 50(4): 814–827. doi: 10.1109/JSSC.2014.2374176
|
[4] |
NAFFZIGER S, BECK N, BURD T, et al. Pioneering chiplet technology and design for the AMD EPYCTM and Ryzentm processor families: Industrial product[C]. IEEE 48th Annual International Symposium on Computer Architecture (ISCA), Valencia, Spain, 2021: 57–70.
|
[5] |
LOH G H, NAFFZIGER S, and LEPAK K. Understanding Chiplets today to anticipate future integration opportunities and limits[C]. 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2021: 142–145.
|
[6] |
GU Qun, XU Zhiwei, KO J, et al. Two 10Gb/s/pin low-power interconnect methods for 3D ICs[C]. 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, San Francisco, USA, 2007: 448–614.
|
[7] |
EVERS M, BARNES L, and CLARK M. The AMD next-generation “Zen 3” core[J]. IEEE Micro, 2022, 42(3): 7–12. doi: 10.1109/MM.2022.3152788
|
[8] |
SU L T, NAFFZIGER S, and PAPERMASTER M. Multi-chip technologies to unleash computing performance gains over the next decade[C]. 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, 2017: 1.1. 1–1.1. 8.
|
[9] |
WANG Xiaoyan and BYUN G S. A 3-D reconfigurable memory I/O interface using a quad-band interconnect[J]. IEEE Transactions on Components, Packaging, and Manufacturing Technology, 2021, 11(5): 832–839. doi: 10.1109/TCPMT.2021.3073594
|
[10] |
蔡志匡, 周国鹏, 宋健, 等. 一种适用于Chiplet测试的通用测试访问端口控制器电路设计[J]. 电子与信息学报, 2023, 45(5): 1593–1601. doi: 10.11999/JEIT220854
CAI Zhikuang, ZHOU Guopeng, SONG Jian, et al. A universal test access port controller circuit design for Chiplet testing[J]. Journal of Electronics &Information Technology, 2023, 45(5): 1593–1601. doi: 10.11999/JEIT220854
|
[11] |
蒋剑飞, 王琴, 贺光辉, 等. Chiplet技术研究与展望[J]. 微电子学与计算机, 2022, 39(1): 1–6. doi: 10.19304/J.ISSN1000-7180.2021.1180
JIANG Jianfei, WANG Qin, HE Guanghui, et al. Research and prospect on Chiplet technology[J]. Microelectronics &Computer, 2022, 39(1): 1–6. doi: 10.19304/J.ISSN1000-7180.2021.1180
|
[12] |
CHENG H C, HUANG T C, HWANG P W, et al. Heat dissipation assessment of Through Silicon Via (TSV)-based 3D IC packaging for CMOS image sensing[J]. Microelectronics Reliability, 2016, 59: 84–94. doi: 10.1016/j.microrel.2015.12.028
|
[13] |
DUKOVIC J, RAMASWAMI S, PAMARTHY S, et al. Through-silicon-via technology for 3D integration[C]. 2010 IEEE International Memory Workshop, Seoul, Korea, 2010: 1–2.
|
[14] |
HAO Wen, SONG Lizhen, JIE Libing, et al. Analysis of typical high speed link based on through silicon via in three-dimensional integration system[C]. 2022 23rd International Conference on Electronic Packaging Technology (ICEPT), Dalian, China, 2022: 1–5.
|
[15] |
SHIBA K, OKADA M, KOSUGE A, et al. A 7-nm FinFET 1.2-TB/s/mm2 3D-stacked SRAM module with 0.7-pJ/b inductive coupling interface using over-SRAM coil and manchester-encoded synchronous transceiver[J]. IEEE Journal of Solid-State Circuits, 2023, 58(7): 2075–2086. doi: 10.1109/JSSC.2022.3224421
|
[16] |
MIZOGUCHI D, YUSOF Y B, MIURA N, et al. A 1.2 Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)[C]. 2004 IEEE International Solid-State Circuits Conference, San Francisco, USA, 2004: 142–517.
|
[17] |
MUTASHAR S, HANNAN M A, SAMAD S A, et al. Analysis and optimization of spiral circular inductive coupling link for bio-implanted applications on air and within human tissue[J]. Sensors, 2014, 14(7): 11522–11541. doi: 10.3390/s140711522
|
[18] |
KAWAI S, ISHIKURO H, and KURODA T. A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card[C]. 2010 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, USA, 2010: 264–265.
|
[19] |
SUKEGAWA S, UMEBAYASHI T, NAKAJIMA T, et al. A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor[C]. 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, USA, 2013: 484–485.
|
[20] |
OIKE Y. Evolution of image sensor architectures with stacked device technologies[J]. IEEE Transactions on Electron Devices, 2022, 69(6): 2757–2765. doi: 10.1109/TED.2021.3097983
|
[21] |
XU Ge, HAYASHI K, ARATA S, et al. A BER-modulated inductive-coupling transceiver using dynamic intermediate interference control technique for low-power communication[C]. 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Chengdu, China, 2018: 69–73.
|
[22] |
潘杰, 杨海钢, 杨立吾. CMOS差分电感和串联电感对的建模与分析[J]. 电子与信息学报, 2009, 31(5): 1264–1267. doi: 10.3724/SP.J.1146.2008.00255
PAN Jie, YANG Haigang, and YANG Liwu. Modeling and analysis of CMOS differential inductors and series-connected inductors[J]. Journal of Electronics &Information Technology, 2009, 31(5): 1264–1267. doi: 10.3724/SP.J.1146.2008.00255
|