A Fault-Tolerant Design of Spaceborne Onboard Neural Network

CHEN Ziyang; ZHANG Meng; ZHANG Jiliang

doi:10.11999/JEIT230378

Volume 45 Issue 9

Sep. 2023

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Article Navigation > Journal of Electronics & Information Technology > 2023 > 45(9): 3234-3243

CHEN Ziyang, ZHANG Meng, ZHANG Jiliang. A Fault-Tolerant Design of Spaceborne Onboard Neural Network[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3234-3243. doi: 10.11999/JEIT230378

Citation:

CHEN Ziyang, ZHANG Meng, ZHANG Jiliang. A Fault-Tolerant Design of Spaceborne Onboard Neural Network[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3234-3243. doi: 10.11999/JEIT230378

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A Fault-Tolerant Design of Spaceborne Onboard Neural Network

doi: 10.11999/JEIT230378

CHEN Ziyang^{1, 2},
ZHANG Meng^{1
,
,},
ZHANG Jiliang³

1.
National Engineering Center of ASIC, Southeast University, Nanjing 210096, China
2.
Nanjing Institute of Electronic Technology, Nanjing 210034, China
3.
College of Computer Science and Electronic Engineering, Hunan University, Changsha 410012, China

Funds: The Key-Area Research and Development Program of Guangdong Province (2021B1101270006), The Natural Science Foundation of Jiangsu Province (BK20201145)

Received Date: 2023-05-05
Accepted Date: 2023-08-21
Rev Recd Date: 2023-08-20

Available Online: 2023-08-24

Publish Date: 2023-09-27

Abstract

Abstract

In order to meet the application requirements of high reliability on-orbit real-time ship target detection, a fault-tolerant reinforcement design for ship target detection based on neural network in Synthetic Aperture Radar (SAR) is proposed. The tiny network MobilenetV2 is used for detection model, which implements the pipeline process in the Field Programmable Gate Array (FPGA). The influence of Single Event Upset (SEU) model on the FPGA is analyzed, which combines the idea of parallelization acceleration and high reliability Triple Module Redundancy (TMR). In this way a partial triple redundancy architecture based on dynamic reconfiguration is designed. The fault-tolerant architecture employs multiple coarse-grained compute units to process multiple images at the same time and uses multi-unit voting to perform single-event flip self-inspection and recovery. The frame rate meets the real-time processing requirements after the real image playback test. By simulating single event upset test, this fault-tolerant design method can improve the detection accuracy of anti-single particle flip by more than 8% when the resource consumption is only increased by less than 20%, which is more suitable for on-orbit applications than the traditional fault-tolerant design method.
- Fault-tolerate design,
- Neural network,
- Field Programmable Gate Array (FPGA),
- Single Event Upset (SEU)

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References(17)

References

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