An Efficient and High-precision Power Consumption Prediction Model for the Register Transfer Level Design Phase

LI Kang; SHI Ruizhi; CHEN Jiawei; SHI Jiangyi; PAN Weitao; WANG Jie

doi:10.11999/JEIT230359

Volume 45 Issue 9

Sep. 2023

Turn off MathJax

Article Contents

Article Navigation > Journal of Electronics & Information Technology > 2023 > 45(9): 3166-3174

LI Kang, SHI Ruizhi, CHEN Jiawei, SHI Jiangyi, PAN Weitao, WANG Jie. An Efficient and High-precision Power Consumption Prediction Model for the Register Transfer Level Design Phase[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3166-3174. doi: 10.11999/JEIT230359

Citation:

LI Kang, SHI Ruizhi, CHEN Jiawei, SHI Jiangyi, PAN Weitao, WANG Jie. An Efficient and High-precision Power Consumption Prediction Model for the Register Transfer Level Design Phase[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3166-3174. doi: 10.11999/JEIT230359

Citation:

LI Kang, SHI Ruizhi, CHEN Jiawei, SHI Jiangyi, PAN Weitao, WANG Jie. An Efficient and High-precision Power Consumption Prediction Model for the Register Transfer Level Design Phase[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3166-3174. doi: 10.11999/JEIT230359

PDF( 3170 KB)

An Efficient and High-precision Power Consumption Prediction Model for the Register Transfer Level Design Phase

doi: 10.11999/JEIT230359

Xidian University, Xi’an 710000, China

Received Date: 2023-05-04
Rev Recd Date: 2023-08-21

Available Online: 2023-08-25

Publish Date: 2023-09-27

Abstract

Abstract

Power consumption is identified as a critical performance objective in circuit design.Existing power estimation tools, such as PrimeTime PX (PTPX), provide high accuracy but are hampered by lengthy execution times and are confined to logic synthesis or physical implementation stages with an already generated netlist. As a result, the need to reduce power analysis time and stress the importance of forward power prediction in chip design has been recognized. A power estimation model for early-stage large-scale Application Specific Integrated Circuit (ASIC) is introduced, which can achieve fast and accurate cycle-level power prediction at the Register Transfer Level (RTL) design stage. The model applies the Smoothly Clipped Absolute Deviation (SCAD) embedding method based on the power correlation principle of input signals for automatic signal selection, addressing the impact of large input feature numbers on estimation performance. A timing alignment method is employed to correct the timing deviation between sign-off level power and RTL-level simulation waveform, enhancing prediction accuracy. The strong nonlinearity of a shallow two-layer convolutional neural network is utilized by the model for power training, consisting of two convolutional layers and one fully connected layer, which reduces computational overhead. Power labels use backend Sign-off level power output data to enhance the accuracy of prediction results.This power estimation model is evaluated on a 28 nm Network Processor(NP) with more than 30 million gates. Experimental results demonstrate that the Mean Absolute Percentage Error (MAPE) of this model for predicting total circuit power consumption is less than 1.71% when compared with the PTPX analysis results following physical design back-annotation. The model takes less than 1.2 s to predict the power curve for 11k clock cycles. In cross-validation experiments with different scenarios, the prediction error of the model is found to be less than 4.5%.
- Power estimation,
- Convolutional Neural Network(CNN),
- Register Transfer Level (RTL),
- Very Large Scale Integration circuit (VLSI)

FullText(HTML)

References(20)

References

[1]	RAUT K J, CHITRE A V, DESHMUKH M S, et al. Low power VLSI design techniques: A review[J]. Journal of University of Shanghai for Science and Technology, 2021, 23(11): 172–183. doi: 10.51201/JUSST/21/11881
[2]	REN Haoxing and HU Jiang. Machine Learning Applications in Electronic Design Automation[M]. Cham: Springer, 2023.
[3]	SROUR M. Data-dependent cycle-accurate power modeling of RTL-level IPs using machine learning[D]. [Master dissertation], The University of Texas at Austin, 2018.
[4]	DHOTRE H, EGGERSGLÜß S, CHAKRABARTY K, et al. Machine learning-based prediction of test power[C]. 2019 IEEE European Test Symposium (ETS), Baden-Baden, Germany, 2019: 1–6.
[5]	NASSER Y, SAU C, PRÉVOTET J C, et al. NeuPow: A CAD methodology for high-level power estimation based on machine learning[J]. ACM Transactions on Design Automation of Electronic Systems, 2020, 25(5): 41. doi: 10.1145/3388141
[6]	ZHOU Yuan, REN Haoxing, ZHANG Yanqing, et al. PRIMAL: Power inference using machine learning[C]. The 56th Annual Design Automation Conference 2019, Las Vegas, USA, 2019: 39.
[7]	KIM D, ZHAO J, BACHRACH J, et al. Simmani: Runtime power modeling for arbitrary RTL with automatic signal selection[C]. The 52nd Annual IEEE/ACM International Symposium on Microarchitecture, Columbus, USA, 2019: 1050–1062.
[8]	XIE Zhiyao, XU Xiaoqing, WALKER M, et al. APOLLO: An automated power modeling framework for runtime power introspection in high-volume commercial microprocessors[C/OL]. MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021: 1–14.
[9]	PUNDIR N, PARK J, FARAHMANDI F, et al. Power side-channel leakage assessment framework at register-transfer level[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022, 30(9): 1207–1218. doi: 10.1109/TVLSI.2022.3175067
[10]	HUANG Guyue, HU Jingbo, HE Yifan, et al. Machine learning for electronic design automation: A survey[J]. ACM Transactions on Design Automation of Electronic Systems, 2021, 26(5): 40. doi: 10.1145/3451179
[11]	FAN Jianqing and LI Runze. Variable selection via nonconcave penalized likelihood and its oracle properties[J]. Journal of the American statistical Association, 2001, 96(456): 1348–1360. doi: 10.1198/016214501753382273
[12]	TIAN Yingjie and ZHANG Yuqi. A comprehensive survey on regularization strategies in machine learning[J]. Information Fusion, 2022, 80: 146–166. doi: 10.1016/j.inffus.2021.11.005
[13]	SCHÜRMANS S, ONNEBRINK G, LEUPERS R, et al. ESL power estimation using virtual platforms with black box processor models[C]. The 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Samos, Greece, 2015: 354–359.
[14]	ZHANG Xianda. Modern Signal Processing[M]. Tsinghua University Press, 2022: 497–564.
[15]	ZHOU Guochang, GUO Baolong, GAO Xiang, et al. A FPGA power estimation method based on an improved BP neural network[C]. 2015 International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP), Adelaide, Australia, 2015: 251–254,
[16]	HE Kaiming, ZHANG Xiangyu, REN Shaoqing, et al. Deep residual learning for image recognition[C]. The 2016 IEEE Conference on Computer Vision and Pattern Recognition, Las Vegas, USA, 2016: 770–778.
[17]	CHHABRIA V A, AHUJA V, PRABHU A, et al. Thermal and IR drop analysis using convolutional encoder-decoder networks[C]. The 26th Asia and South Pacific Design Automation Conference, Tokyo, Japan, 2021: 690–696.
[18]	FARAWAY J J. Linear Models with R[M]. 2nd ed. New York: CRC Press, 2014.
[19]	JEON H and OH S. Hybrid-recursive feature elimination for efficient feature selection[J]. Applied Sciences, 2020, 10(9): 3211. doi: 10.3390/app10093211
[20]	XUAN Yi, SI Weiguo, ZHU Zhu, et al. Multi-model fusion short-term load forecasting based on random forest feature selection and hybrid neural network[J]. IEEE Access, 2021, 9: 69002–69009. doi: 10.1109/ACCESS.2021.3051337