Design of an Process In-Memory Full Adder Based on Voltage-Controlled Spin Orbit Torque Magnetic Random Access Memory

LIU Xiao; LIU Dijun; ZHANG Youguang; LUO Lichuan; KANG Wang

doi:10.11999/JEIT230306

Volume 45 Issue 9

Sep. 2023

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Article Navigation > Journal of Electronics & Information Technology > 2023 > 45(9): 3228-3233

LIU Xiao, LIU Dijun, ZHANG Youguang, LUO Lichuan, KANG Wang. Design of an Process In-Memory Full Adder Based on Voltage-Controlled Spin Orbit Torque Magnetic Random Access Memory[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3228-3233. doi: 10.11999/JEIT230306

Citation:

LIU Xiao, LIU Dijun, ZHANG Youguang, LUO Lichuan, KANG Wang. Design of an Process In-Memory Full Adder Based on Voltage-Controlled Spin Orbit Torque Magnetic Random Access Memory[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3228-3233. doi: 10.11999/JEIT230306

Citation:

LIU Xiao, LIU Dijun, ZHANG Youguang, LUO Lichuan, KANG Wang. Design of an Process In-Memory Full Adder Based on Voltage-Controlled Spin Orbit Torque Magnetic Random Access Memory[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3228-3233. doi: 10.11999/JEIT230306

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Design of an Process In-Memory Full Adder Based on Voltage-Controlled Spin Orbit Torque Magnetic Random Access Memory

doi: 10.11999/JEIT230306

1.
School of Electronic and Information Engineering, Beihang University, Beijing 100191, China
2.
School of Integrated Circuit Science and Engineering, Beihang University, Beijing 100191, China

Received Date: 2023-04-19
Accepted Date: 2023-08-17
Rev Recd Date: 2023-08-16

Available Online: 2023-08-22

Publish Date: 2023-09-27

Abstract

Abstract

With the feature size of complementary metal oxide semiconductor technology decreasing, the problem of static power consumption becomes more and more serious. Spin Magnetic Random Access Memory (MRAM) has been widely studied because of its nonvolatile, high-speed read-write ability, high integration density and CMOS compatibility. In this paper, a reconfigurable memory logic array is designed using a novel Voltage-Controlled Spin-Orbit Torque(VC-SOT) random access memory. It can implement all of Boolean Logic functions and highly parallel computing. On this basis, an in-memory computing Full Adder (FA) is designed and simulated in 40 nm process. The results show that the proposed full adder has higher parallelism, faster computation speed (～1.11 ns/bit) and lower computation power consumption (～5.07 fJ/bit).
- Full adder,
- Process In-Memory,
- Spin orbital torque,
- Magnetic tunnel junction,
- Reconfigurable

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References(18)

References

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