Design of a Low-area and Low-delay Triple-Node-Upset Tolerant Latch

YAN Aibin; SHEN Zhen; CUI Jie; HUANG Zhengfeng

doi:10.11999/JEIT230114

Volume 45 Issue 9

Sep. 2023

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Article Navigation > Journal of Electronics & Information Technology > 2023 > 45(9): 3272-3283

YAN Aibin, SHEN Zhen, CUI Jie, HUANG Zhengfeng. Design of a Low-area and Low-delay Triple-Node-Upset Tolerant Latch[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3272-3283. doi: 10.11999/JEIT230114

Citation:

YAN Aibin, SHEN Zhen, CUI Jie, HUANG Zhengfeng. Design of a Low-area and Low-delay Triple-Node-Upset Tolerant Latch[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3272-3283. doi: 10.11999/JEIT230114

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Design of a Low-area and Low-delay Triple-Node-Upset Tolerant Latch

doi: 10.11999/JEIT230114

YAN Aibin^{1, 2},
SHEN Zhen^{1
,
,},
CUI Jie¹,
HUANG Zhengfeng²

1.
School of Computer Science and Technology, Anhui University, Hefei 230601, China
2.
School of Microelectronics, Hefei University of Technology, Hefei 230601, China

Funds: The National Natural Science Foundation of China (62274052, 61974001)

Received Date: 2023-02-28
Rev Recd Date: 2023-07-04

Available Online: 2023-07-11

Publish Date: 2023-09-27

Abstract

Abstract

With the continuous development of nanoscale CMOS integrated circuits, latches are extremely susceptible to harsh radiation environment, and the multiple-node upset caused by radiation is becoming more and more serious. A Triple Node Upset (TNU) tolerant latch based on Dual-Interlocking CElls (DICEs) and dual-level C-elements is proposed. It includes five transmission gates, two DICEs, and three C-elements. The latch has a small number of transistors, which reduces greatly the hardware overhead of the latch to ensure low cost. Each DICE can be used to tolerate and recover from single-node upset, and the C-element has an error interception feature to mask erroneous values from DICEs. When any three nodes of the latch are upset, the latch can tolerate the TNU with the help of DICEs and C-elements. The simulation results using H-Simulation Program with Integrated Circuit Emphasis (HSPICE) show that, compared with the most advanced TNU tolerant latch designs, the delay is reduced by 64.65%, and the delay power area product is reduced by 65.07% for the proposed latch on average.
- Latch,
- Triple Node Upset (TNU),
- Radiation hardening by design,
- C-element,
- Dual-Interlocked-storage-CEll (DICE)

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References(22)

References

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