Design of Hybrid-granularity Multifunctional Computing Unit Based on And-Xor-Inv Graph

DAI Zibin; ZHANG Zongren; LIU Yanjiang; ZHOU Zhaoxu; JIANG Danping

doi:10.11999/JEIT230021

Volume 45 Issue 9

Sep. 2023

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Article Navigation > Journal of Electronics & Information Technology > 2023 > 45(9): 3370-3379

DAI Zibin, ZHANG Zongren, LIU Yanjiang, ZHOU Zhaoxu, JIANG Danping. Design of Hybrid-granularity Multifunctional Computing Unit Based on And-Xor-Inv Graph[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3370-3379. doi: 10.11999/JEIT230021

Citation:

DAI Zibin, ZHANG Zongren, LIU Yanjiang, ZHOU Zhaoxu, JIANG Danping. Design of Hybrid-granularity Multifunctional Computing Unit Based on And-Xor-Inv Graph[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3370-3379. doi: 10.11999/JEIT230021

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Design of Hybrid-granularity Multifunctional Computing Unit Based on And-Xor-Inv Graph

doi: 10.11999/JEIT230021

1.
School of Cryptography, Information Engineering University, Zhengzhou 450000, China
2.
Unit 31642 of PLA, Lincang 677000, China

Funds: National Science and Technology Major Project of China (2018ZX01027101-004)

Received Date: 2023-01-16
Rev Recd Date: 2023-04-13

Available Online: 2023-04-27

Publish Date: 2023-09-27

Abstract

Abstract

Recently, the majority of fine-grained sequence-coding algorithms are not applied to the existing Coarse-Grained ReConfigurable Arrays (CGRCA). Moreover, competition conflicts often occur in the encoding stages, which causes low resource utilization and high latency for CGRCA. To address this issue, a Hybrid-grained Reconfigurable Multifunctional Cryptographic Arithmetic unit (RHMCA) at transistor-level is proposed in this paper, which can be compatible with non-linear Boolean functions in existing stream cryptography algorithms with improved performance metrics. More specifically, a Reconfigurable And-Xor-Nand (RAXN) logic element based on the And-Xor-Inv Graph (AXIG) logic is designed, which can reconfigure the several logic functions (including the And, Xor, and Nand). A transistor-level implementation and layout structure of RAXN is proposed to reduce the delay overhead; A functional extension method of RAXN is proposed in this paper and a basic functional Unit (RAXN_U) is proposed to realize full adder, three-input And/Xor logic, and multiplier partial product generation functions; A hybrid-grained RHMCA is designed by combining the interconnect resources and RAXN_Us in the array, which can implement 32 bit addition, 8 bit multiplication, CF(2⁸) finite field multiplication, and complex nonlinear Boolean functions. The proposed design is validated with the CMOS 40 nm technology, and the results show that the proposed design reduces 1.27 ns delay and decreases 44.8% Area-Delay Product (ADP) value compared to the existing approaches.
- Cryptographic operation unit,
- Multifunctional reconfiguration,
- Mixed granularity,
- And-Xor-Inv Graph (AXIG)

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References(20)

References

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