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Volume 45 Issue 9
Sep.  2023
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YAN Xinkai, DING Sheng. Adaptive Image Interpolation Algorithm and Acceleration Engine Co-Design[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3284-3294. doi: 10.11999/JEIT221503
Citation: YAN Xinkai, DING Sheng. Adaptive Image Interpolation Algorithm and Acceleration Engine Co-Design[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3284-3294. doi: 10.11999/JEIT221503

Adaptive Image Interpolation Algorithm and Acceleration Engine Co-Design

doi: 10.11999/JEIT221503
Funds:  The Natural Science Foundation of the Jiangsu Higher Education Institutions of China (19KJB510027), Jiangsu “333” Scientific Research Project (BRA2020318), The Development Fundation of Jiangsu Key Laboratory of Asic Design (2020KLOP005)
  • Received Date: 2022-12-02
  • Rev Recd Date: 2023-04-12
  • Available Online: 2023-04-19
  • Publish Date: 2023-09-27
  • In order to improve the super-resolution reconstruction effect of the high-definition color image, a new adaptive image interpolation algorithm based on edge contrast is proposed, which chooses adaptively the coefficients of Lanczos interpolation by edge contrast detection and receptive fields with different scales. Adaptability and diverse receptive fields can further improve the quality of image magnification. Compared with the bilinear interpolation algorithm, the Peak Signal to Noise Ratio (PSNR), Structural SIMilarity (SSIM) and Learned Perceptual Image Patch Similarity (LPIPS) are improved by 1.1 dB, 0.025, 0.051, respectively. Compared with the bicubic interpolation algorithm, the PSNR, SSIM and LPIPS are improved by 0.34 dB, 0.01, 0.033, respectively. Moreover, in order to reduce the hardware resources and improve the storage efficiency, a high parallelized and high efficiency accelerated architecture is proposed. A 2-level data reuse and coefficients pulsation mechanism are employed to improve the computation-memory access ratio greatly. The synthesis result of the acceleration engine in the 16nm process library can reach the 2 GHz clock frequency. The operating frequency of FPGA project deployed in Xilinx Zynq Ultra scale+ xczu15eg can reach up to 200 MHz as well, which means that the algorithm can adapt to the frame rate (fps) up to 60.
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