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Volume 45 Issue 9
Sep.  2023
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GUO Zhenjiang, WANG Huandong, ZHANG Fuxin, XIAO Junhua. Deadlock Avoidance of Advanced eXtensible Interface Interconnection Networks in Modular System-on-Chips[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3175-3183. doi: 10.11999/JEIT221142
Citation: GUO Zhenjiang, WANG Huandong, ZHANG Fuxin, XIAO Junhua. Deadlock Avoidance of Advanced eXtensible Interface Interconnection Networks in Modular System-on-Chips[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3175-3183. doi: 10.11999/JEIT221142

Deadlock Avoidance of Advanced eXtensible Interface Interconnection Networks in Modular System-on-Chips

doi: 10.11999/JEIT221142
Funds:  The Strategic Priority Research Program of the Chinese Academy of Sciences (XDC05020000)
  • Received Date: 2022-09-01
  • Rev Recd Date: 2023-01-16
  • Available Online: 2023-02-03
  • Publish Date: 2023-09-27
  • Modular System-on-Chips (MSoC) contain several distinct IP components with possibly multiple sub-networks, resulting in potential deadlock situations for the Network on Chip (NoC). A MSoC is developed, and three deadlock cases in Advanced eXtensible Interface (AXI)-based network-on-chip are studied. MSoC consists of various common heterogeneous components, and NoC integrated by multiple independent subnetworks. MSoC can fully reflect the complexity and irregularity of real chips. NoC based on AXI is found toface double-path deadlock and bridge deadlock in addition to loop-path deadlock. A two-stage algorithm is proposed to detect those three cases. Compared to Universal Verification Methodology(UVM) random verification, this method can reduce detection time from months to hours, improving the reliability and robustness of the on-chip network.
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