新型CMOS JK触发器
Novel CMOS JK Flip-Flop
-
摘要: 该文以双反相器闩锁电路为基本存贮单元,采用开关级设计方法设计出一种新型的CMOS JK触发器。与传统设计相比,新设计具有较简单的结构、较少的元件以及较快的工作速度。
-
关键词:
- CMOS; JK触发器; 开关级设计
Abstract: Taking the latch composed of two inverters as basic storage unit, this paper proposes a novel CMOS JK flip-flop based on the design at switch level. The new design has simpler configuration with less devices and faster working speed in comparing with the traditional design. -
Telllez G E, Farrah A, Sarrafzadeh M. Activity-driven clock design for low power circuits. Proc. IEEE ICCD, TX, USA, 1995,11: 62- 65.[2]王伦耀,吴训威.主从型D触发器的动态功耗分析.浙江大学学报(理学版), 2003,30(1):35-40.[3]Wu X (吴训威), Wei J (韦健). CMOS edge-triggered flip-flop using one latch[J].Electron. Lett.1998, 34 (16):1581-[4]Wu X (吴训威). Theory of transmission switches and its application to design of CMOS digital circuits[J].International Journal of Circuit Theory and Application.1992, 20(4):349-[5]Rabaey J M. Digital Integrated Circuits: A Design Perspective.New York: Prentice-Hall Inc. 1996:60 - 62. -
计量
- 文章访问数: 2517
- HTML全文浏览量: 182
- PDF下载量: 969
- 被引次数: 0
下载:
