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Volume 28 Issue 7
Jan.  2011
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Gao Xue-lian, Shi Yin. A Data Array Description Method in Automatic Synthesis of Analog Circuit[J]. Journal of Electronics & Information Technology, 2006, 28(7): 1340-1344.
Citation: Gao Xue-lian, Shi Yin. A Data Array Description Method in Automatic Synthesis of Analog Circuit[J]. Journal of Electronics & Information Technology, 2006, 28(7): 1340-1344.

A Data Array Description Method in Automatic Synthesis of Analog Circuit

  • Received Date: 2004-11-25
  • Rev Recd Date: 2005-06-07
  • Publish Date: 2006-07-19
  • This paper presents an analog circuit data array description method and circuit-constructing rules that coordinately work with description language. With the prerequisite of no invalid circuit structure, circuit-constructing rules create high quality op-amp circuit structure. This new technique, starting from classic sub-circuit model, automatically creating op-amp circuit, guarantees the quality of circuit construction. Results are reported to validate the effectiveness of this approach for construction-design automation of op-amp circuit.
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  • Goh C, li Y. GA automated design and synthesis of analog circuitswith practical constraints, 2001. Proceedings of the 2001Congress on Evolutionary Computation, Seoul, Korea, 27-30 May,2001, Vol. 1: 170 . 177 .[2]Papa G, Silc J. Automatic large-scale integrated circuit synthesisusing allocation-based scheduling algorithm, Microprocessorsand Microsystems, 2002, 26(3): 139 . 147.[3]Koh H Y, Sequin C H, Gray P R. OPASYN:A compiler forCMOS operational amplifiers[J].IEEE Trans. on Computer-AidedDesign of Integrated Circuits and Systems.1990, 9(2):113-[4]Gupta S K, Hasan M M. KANSYS: A CAD tool for analog circuitsynthesis. 9th International Conference on VLSI Design,Bangalore, India, Jan. 1996: 333 . 334.[5]El-Turky F, Perry E E. BLADES: An artificial intelligenceapproach to analog circuit design[J].IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems.1989, 8(6):680-[6]Makris C A, et al.. CHIPAIED: A new approach to analogueintegrated circuit design. IEE Colloquium on Analogue VLSI,London,UK,10 May, 1990: 1/1 . 111.[7]Lohn J D, Colombano S P. A circuit representation technique forautomated circuit design. IEEE Trans. on EvolutionaryComputation, 1999, 3(3): 205 . 219.[8]Prakobwaitayakit K, Fujii N. A neural network approach to circuittopology generator. The 2000 IEEE Asia-Pacific Conference onCircuits and Systems, Tianjin, China, 4-6 Dec., 2000: 93 . 96.
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