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Volume 24 Issue 2
Feb.  2002
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Lno Feng, Wu Shunjun, Song Wanjie . ASIC design and CPLD implementation for DWT decomposition[J]. Journal of Electronics & Information Technology, 2002, 24(2): 280-284.
Citation: Lno Feng, Wu Shunjun, Song Wanjie . ASIC design and CPLD implementation for DWT decomposition[J]. Journal of Electronics & Information Technology, 2002, 24(2): 280-284.

ASIC design and CPLD implementation for DWT decomposition

  • Received Date: 1999-07-21
  • Rev Recd Date: 1999-12-01
  • Publish Date: 2002-02-19
  • The wavelet transform is a very effective mathematical tools for many fields such as signal processing and image coding, which is implemented by program in most cases. This paper presents a novel architecture suitable with CPLD chip for one- dimension DWT decomposition based on the relationship between wavelet transform and filter banks by rearranging the data in the processing of convolution and downsample by two. It possesses some practicable value with certain speed and decreased resources.
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  • Wu Xiaodong et al., Programmable wavelet packet transform processor, Electron. Lett., 1999,35(6), 449-450.[2]Keshab K. Parhi, Takao Nishitani, VLSI architectures for discrete wavelet transform, IEEE Trans.on VLSI Syst., 1993, 1(2), 191-202.[3]S. G. Mallat, Multifrequency channels decomposition of inages and wavelet models, IEEE Trans.on ASSP, 1989, ASSP-37(12), 2091-2110.[4]Oliver Rioul, Pierre Duhamel, Fast algorithms for discrete and continuous wavelet transforms,IEEE Trans on IT, 1992, IT-38(2), 569-586.[5]宋万杰,罗丰,吴顺君,CPLD技术原理及应用,西安,西安电子科技大学出版社,1999,9 .
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