Sun Huajin, Gao Deyuan, Zhang Shengbing. The FPGA implementation of the round robin scheduling algorithms[J]. Journal of Electronics & Information Technology, 2003, 25(8): 1143-1147.
Citation:
Sun Huajin, Gao Deyuan, Zhang Shengbing. The FPGA implementation of the round robin scheduling algorithms[J]. Journal of Electronics & Information Technology, 2003, 25(8): 1143-1147.
Sun Huajin, Gao Deyuan, Zhang Shengbing. The FPGA implementation of the round robin scheduling algorithms[J]. Journal of Electronics & Information Technology, 2003, 25(8): 1143-1147.
Citation:
Sun Huajin, Gao Deyuan, Zhang Shengbing. The FPGA implementation of the round robin scheduling algorithms[J]. Journal of Electronics & Information Technology, 2003, 25(8): 1143-1147.
Round robin scheduling algorithm is a classic scheduling algorithm with many ap-plications. An FPGA implementation by using barrel shifter and pipelined priority encoder is presented in this paper with considering the FPGA structure characteristic and systems requirement. And the performance and resource consumption of the implementation are dis-cussed. The test result shows that the implementation of the algorithm is effective and fit for the FPGA structure. The system with the implementation of algorithm runs very well.
M.G.H. Katevenis, Fast switching and fair control of congested flow in broadband networks,IEEE on Selected Areas Comm., 1987, SAC-5(8), 1315-1326.[2]The Programmable Logic Data Book 2000, Xilinx Incorporation, 2000, Section 3.[3]夏宇闻,复杂数字电路与系统的Verilog HDL设计技术,北京,北京航空航天大学出版社,1998,第二章,第四章.
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