A HIGH ORDER ALL DIGITAL PHASE LOCKED LOOP WITH TANDEM STRUCTURE

Shi Fujiang; Lin Xiaokang; Feng Zhongxi

Volume 21 Issue 5

Sep. 1999

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Shi Fujiang, Lin Xiaokang, Feng Zhongxi. A HIGH ORDER ALL DIGITAL PHASE LOCKED LOOP WITH TANDEM STRUCTURE[J]. Journal of Electronics & Information Technology, 1999, 21(5): 640-645.

Citation:

Shi Fujiang, Lin Xiaokang, Feng Zhongxi. A HIGH ORDER ALL DIGITAL PHASE LOCKED LOOP WITH TANDEM STRUCTURE[J]. Journal of Electronics & Information Technology, 1999, 21(5): 640-645.

Shi Fujiang, Lin Xiaokang, Feng Zhongxi. A HIGH ORDER ALL DIGITAL PHASE LOCKED LOOP WITH TANDEM STRUCTURE[J]. Journal of Electronics & Information Technology, 1999, 21(5): 640-645.

Citation:

Shi Fujiang, Lin Xiaokang, Feng Zhongxi. A HIGH ORDER ALL DIGITAL PHASE LOCKED LOOP WITH TANDEM STRUCTURE[J]. Journal of Electronics & Information Technology, 1999, 21(5): 640-645.

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A HIGH ORDER ALL DIGITAL PHASE LOCKED LOOP WITH TANDEM STRUCTURE

Received Date: 1998-03-16
Rev Recd Date: 1998-11-16
Publish Date: 1999-09-19

Abstract

Abstract

A high order all digital phase locked loop with tandem structure is presented. A 2-order all digital PLL is implemented and its performance is verified by simulation. An example is given for SDH 2048Kb/s tributary recovery. Its performances are simulated and compared with the theoretical analysis.

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References(1)

References

Loau Chii-Min, Wu Ji-Tsu. PHDPLL for SONET desynchronzer. GLOBECOM91, Phoenix, USA: 1991, 402-405.[2]ITU-T Recommendation G.783(Draft), Characteristics of synchronous digital hierarchy(SDH)[3]equipment functional blocks, 12.04.1997.[4]ITU-T Recommendation 6.823, The control of jitter and wander within digital networks which are based on the SDH, 1992.[5]张厥盛, 郑继禹, 万心平. 锁相技术西安:西安电子科技大学出版社, 1994，第七章, 第一节.[6]Hiknet Sari, et al. Cancellation of pointer adjustment jitter in SDH network. IEEE Trans. on Communications, 1994, COM-42(12): 3200-3207.[7]Kusyk R G, et al. Analysis of techniques for the reduction of jitter caused by SONET pointer adjustments. IEEE Trans. on Communications, 1994, COM-42(2/3/4): 2036-2050.[8]Transwitch Data Sheet, ADMA-El 2Mbit/s to TU-12 asynchronous mapper/desynchronizer, TXC-04002-MB, Ed.3A, August 1995.

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