DEEP LEVEL DEFECTS IN Si-IMPLANTED LEC UNDOPED SI-GaAs

Liang Zhenxian; Luo Jinsheng

Volume 13 Issue 1

Jan. 1991

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Article Navigation > Journal of Electronics & Information Technology > 1991 > 13(1): 65-70

Liang Zhenxian, Luo Jinsheng. DEEP LEVEL DEFECTS IN Si-IMPLANTED LEC UNDOPED SI-GaAs[J]. Journal of Electronics & Information Technology, 1991, 13(1): 65-70.

Citation:

Liang Zhenxian, Luo Jinsheng. DEEP LEVEL DEFECTS IN Si-IMPLANTED LEC UNDOPED SI-GaAs[J]. Journal of Electronics & Information Technology, 1991, 13(1): 65-70.

Liang Zhenxian, Luo Jinsheng. DEEP LEVEL DEFECTS IN Si-IMPLANTED LEC UNDOPED SI-GaAs[J]. Journal of Electronics & Information Technology, 1991, 13(1): 65-70.

Citation:

Liang Zhenxian, Luo Jinsheng. DEEP LEVEL DEFECTS IN Si-IMPLANTED LEC UNDOPED SI-GaAs[J]. Journal of Electronics & Information Technology, 1991, 13(1): 65-70.

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DEEP LEVEL DEFECTS IN Si-IMPLANTED LEC UNDOPED SI-GaAs

Liang Zhenxian^{①②;罗晋生},
Luo Jinsheng

Received Date: 1989-10-14
Rev Recd Date: 1990-02-26
Publish Date: 1991-01-19

Abstract

Abstract

DLTS technique has becn used to investigate (4 1012cm-2/30keV+5 1012cm-2/ 130keV)Si implanted LEC undoped SI-GaAs annealed by tow-step rapid thermal annealing (RTA) (970℃/9s +750℃/12s). Two electron traps ET1(Ec- 0.53 eV, 2.3 10-16cm2) and ET2(Ec-0.81eV, 9.710-13cm2) are detected. Furthermore, the noticeable variations of trap s concentration and energy level in the forbidden gap with the depth profile of defects induced by ion implantation and RTA processes have been observed, The [Asi VAsAsGa] and [VAsAsiVGaAsGa] are proposed as the possible atomic configurations of ET1,and ET2 respectively to explain their RTA behavior.

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References(1)

References

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