Novel CMOS JK Flip-Flop

Wu Xun-wei; Wang Peng-jun; Shen Yan-fei

Volume 27 Issue 2

Feb. 2005

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Article Navigation > Journal of Electronics & Information Technology > 2005 > 27(2): 334-336

Wu Xun-wei, Wang Peng-jun, Shen Yan-fei. Novel CMOS JK Flip-Flop[J]. Journal of Electronics & Information Technology, 2005, 27(2): 334-336.

Citation:

Wu Xun-wei, Wang Peng-jun, Shen Yan-fei. Novel CMOS JK Flip-Flop[J]. Journal of Electronics & Information Technology, 2005, 27(2): 334-336.

Wu Xun-wei, Wang Peng-jun, Shen Yan-fei. Novel CMOS JK Flip-Flop[J]. Journal of Electronics & Information Technology, 2005, 27(2): 334-336.

Citation:

Wu Xun-wei, Wang Peng-jun, Shen Yan-fei. Novel CMOS JK Flip-Flop[J]. Journal of Electronics & Information Technology, 2005, 27(2): 334-336.

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Novel CMOS JK Flip-Flop

Received Date: 2003-06-10
Rev Recd Date: 2004-09-22
Publish Date: 2005-02-19

Abstract

Abstract

Taking the latch composed of two inverters as basic storage unit, this paper proposes a novel CMOS JK flip-flop based on the design at switch level. The new design has simpler configuration with less devices and faster working speed in comparing with the traditional design.

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References(1)

References

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