Qiao Lu-feng, Wang Zhi-gong, Huang Bin, Lu Yuan-lin . Implementation of PCI Bus Multi-user Data Buffer Manager[J]. Journal of Electronics & Information Technology, 2005, 27(7): 1162-1166.
Citation:
Qiao Lu-feng, Wang Zhi-gong, Huang Bin, Lu Yuan-lin . Implementation of PCI Bus Multi-user Data Buffer Manager[J]. Journal of Electronics & Information Technology, 2005, 27(7): 1162-1166.
Qiao Lu-feng, Wang Zhi-gong, Huang Bin, Lu Yuan-lin . Implementation of PCI Bus Multi-user Data Buffer Manager[J]. Journal of Electronics & Information Technology, 2005, 27(7): 1162-1166.
Citation:
Qiao Lu-feng, Wang Zhi-gong, Huang Bin, Lu Yuan-lin . Implementation of PCI Bus Multi-user Data Buffer Manager[J]. Journal of Electronics & Information Technology, 2005, 27(7): 1162-1166.
The circuit structure of a kind of PCI bus multi-user data Buffer Manager (BM) is analyzed in this paper, and typical simulating waveform is presented. The method to allocate the data buffers, port bandwidth, maximum user waiting time and minimum user buffer requirements are analyzed theoretically. The expression to calculate the minimum memory needed in the BM is given. Based on the analysis, a 128-user buffer manager is realized with XILINX XCV600EPQ240 and verified in application systems.
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