SYSTOLIC ARRAY DESIGN FOR 2-D CONVOLUTIONS WITH BIG KERNEL IN LOW-RANK

Yang Luxi; Wang Baoyun; He Zhenya

Volume 19 Issue 1

Jan. 1997

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Yang Luxi, Wang Baoyun, He Zhenya. SYSTOLIC ARRAY DESIGN FOR 2-D CONVOLUTIONS WITH BIG KERNEL IN LOW-RANK[J]. Journal of Electronics & Information Technology, 1997, 19(1): 6-10.

Citation:

Yang Luxi, Wang Baoyun, He Zhenya. SYSTOLIC ARRAY DESIGN FOR 2-D CONVOLUTIONS WITH BIG KERNEL IN LOW-RANK[J]. Journal of Electronics & Information Technology, 1997, 19(1): 6-10.

Yang Luxi, Wang Baoyun, He Zhenya. SYSTOLIC ARRAY DESIGN FOR 2-D CONVOLUTIONS WITH BIG KERNEL IN LOW-RANK[J]. Journal of Electronics & Information Technology, 1997, 19(1): 6-10.

Citation:

Yang Luxi, Wang Baoyun, He Zhenya. SYSTOLIC ARRAY DESIGN FOR 2-D CONVOLUTIONS WITH BIG KERNEL IN LOW-RANK[J]. Journal of Electronics & Information Technology, 1997, 19(1): 6-10.

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SYSTOLIC ARRAY DESIGN FOR 2-D CONVOLUTIONS WITH BIG KERNEL IN LOW-RANK

Received Date: 1995-03-02
Rev Recd Date: 1995-08-30
Publish Date: 1997-01-19

Abstract

Abstract

The characteristics of 2-D convolutions with big kernel in low-rank are analysed, and a fast algorithm is given. Then a systolic array implementation, which is derived by a three-stage dependence-graph-based mapping approach, is presented. It is shown that the architecture has a high efficiency for parallel processing and a nearly linear speed-up.

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References(1)

References

Kung H T, Lam M S. J. Parallel and Distributed Computting, 1984, 1(1): 32-63.[2]De Vos L, Stegherr M. A Family of Application-Specific VLSI Architecture for the Block-Matching[3]Algorithm. in Systolic Array Processors, J.McCanny, J.Mcwhirter, E.Swartzlander, ed., Hertford-shire: Prentice-Hall, Inc., 1989, 421-430.[4]Bombardieri J. IEEE Trans. on Signal Processing, 1992, SP-40(5): 1253-1257.[5]Kung S Y. VLSI Array Processors, Englewood Cliffs: Prentice-Hall, Inc., 1988, 119-211.

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