A METHODOLOGY OF HIGH-LEVEL TECHNOLOGY MAPPING BASED ON KNOWLEDGE

马聪.刘明业等, VHDL高级综合与底层物理设计的衔接,电子学报, 1998,26(2),71-73.[2]R.Ang.N.Dutt,An algorithm for allocation of functional units from realistic RT component libraries,7th Int.Symp.High-Level Synth,1994,164-169.[3]E.A.Rundensteiner,D.D.Gajski,Component synthesis form function descriptions,IEEE Trans.on CAD,ICSyst.,1993,12(9),1287-1299.[4]刘明业等,专用集成电路(ASIC)高级综合理论,北京,北京理工大学出版社,1997,179-238,307-366.[5]R.K.Brayton,R.Camposano et al.The Yorktown Silicon Compiler,In Slicaon Compilation,D.D.Gajski(Ed),Addison-Wesley,Reading,MA,1988,204-311.[6]Gwo-Dong Chen,D.D.Gajski,An intelligent component database for behavioral synthesis,Proc.of the 27th Design Automation Conference,IEEE/ACM,Orlando Florida,1990,150-155.[7]N.V.Zanden,D.Gajski,MILO:A microarchitecture and logic optimizer,Proc.of the 25th Design Automation Conference,IEEE/ACM,Anaheim Convevtion Center,1998,403-408.[8]A.R.Baseer,M.Balakreshnan et al,FAST:FPGA Targeted RTL structure synthesis technique,7th International Conference on VLSI Design Calcutta,Idia. [9]A.R.Naseer.M.Balakrishnan et al[J].,Delay minimal mapping RTL structures onto LUT based FPGAs:Field Programmable Logic and Applications,5th International workshop,FPL95,Proceddings,Oxford,UK,29 Aug-1 Sept.1994,1995:139-141[9]M.Vootukuru,R.Vemuri et al.,Resource constrained RTL partition for synthesis of multi-FPGA designs,Proceedings Tenth International Conference on VLSI Design,Hyderabad,India,4-7 Jan,1997,140-144.[10]Sri Parameswaran,M.F.Schulz M.F,Computer-aided selection of components for technology-Independent specifications,IEEE Trans.on Comput-Aided Des.Integr.Circuits Syst.,1994,13(11),1333-1350.[11]P.K.Jha,N.D.Dute,High-level library mapping for arithmetic components,IEEE Trans.on VLSI Syst.,1996,4(2),157-169.[12]马聪,王作建,刘明业, VHDL高级综合系统中多层次.多目标工艺映射策略及其实现,计算机学报, 1999,22(9),975-988.