Xiang Hui, Teng Jianfu, Wang Chengning. A REAL-TIME 2-D DCT/IDCT PROCESSOR USING FPGAs[J]. Journal of Electronics & Information Technology, 1999, 21(6): 797-805.
Citation:
Xiang Hui, Teng Jianfu, Wang Chengning. A REAL-TIME 2-D DCT/IDCT PROCESSOR USING FPGAs[J]. Journal of Electronics & Information Technology, 1999, 21(6): 797-805.
Xiang Hui, Teng Jianfu, Wang Chengning. A REAL-TIME 2-D DCT/IDCT PROCESSOR USING FPGAs[J]. Journal of Electronics & Information Technology, 1999, 21(6): 797-805.
Citation:
Xiang Hui, Teng Jianfu, Wang Chengning. A REAL-TIME 2-D DCT/IDCT PROCESSOR USING FPGAs[J]. Journal of Electronics & Information Technology, 1999, 21(6): 797-805.
Based on the skew-circular convolution distributed algorithm presented by W.Li(1991). A 88 2-D DCT/IDCT processor has been designed using FPGAs, which can be used for HDTV s decoder or other signal and information processing systems. It can be used to calculate either DCT or IDCT depending on a single control line. AM of the input/output are 12-bit and the internal data bus and internal parameters are 16-bit.
卢煊.等.基于FPGA的实时高速二维DCT/IDCT处理器.徽电子学.1996,(1): 15-19.[2] Li W. A New Algorithm to Compute the DCT and its Inverse. IEEE Trans.on SP, 1991, SP-39(6): 1305-1313.[2]Xilinx Inc. The Programmable Logic Data Book. 1993.[3]孟宪元可编程专用集成电路原理、设计和应用电子工业出版社, 1995.
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