VERIFICATION DESIGNING FOR SYNCHRONOUS CIRCUITS

He Xinhua; Lu Changling; Gong Yunzhan

Volume 19 Issue 4

Jul. 1997

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Article Navigation > Journal of Electronics & Information Technology > 1997 > 19(4): 532-537

He Xinhua, Lu Changling, Gong Yunzhan. VERIFICATION DESIGNING FOR SYNCHRONOUS CIRCUITS[J]. Journal of Electronics & Information Technology, 1997, 19(4): 532-537.

Citation:

He Xinhua, Lu Changling, Gong Yunzhan. VERIFICATION DESIGNING FOR SYNCHRONOUS CIRCUITS[J]. Journal of Electronics & Information Technology, 1997, 19(4): 532-537.

He Xinhua, Lu Changling, Gong Yunzhan. VERIFICATION DESIGNING FOR SYNCHRONOUS CIRCUITS[J]. Journal of Electronics & Information Technology, 1997, 19(4): 532-537.

Citation:

He Xinhua, Lu Changling, Gong Yunzhan. VERIFICATION DESIGNING FOR SYNCHRONOUS CIRCUITS[J]. Journal of Electronics & Information Technology, 1997, 19(4): 532-537.

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VERIFICATION DESIGNING FOR SYNCHRONOUS CIRCUITS

Received Date: 1995-03-06
Rev Recd Date: 1995-10-31
Publish Date: 1997-07-19

Abstract

Abstract

It is very effective that use BDD to describe the synchronous circuits. This paper has proposed the reducing way for BDD in order to collapse the number of inputs, routes and states. Based on the features of circuit, several heuristic methods that speed up verification are presented.

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References(1)

References

Odawara G.[J].et al. A logic verifier based on Boolean comparison, DA8.1986,:-. A logic verifier based on Boolean comparison, DA' target='_blank'>[2]Bose S.[J].Fisher A L. Automatic verification of synchronous circuits using symbolic logic simulation and temporal logic, IFIP9.1990,:-Touati H J.[J].et al.Implicit state enumeration of finite state machine using BDDs, ICCAD9.1990,:-.Implicit state enumeration of finite state machine using BDD' target='_blank'>

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