CAPACITANCE EXTRACTION OF THE VIA HOLE STRUCTURE EMBEDDED IN THE MULTILAYERED DIELECTRIC MEDIA

Song Ben; Hong Wei

Volume 20 Issue 1

Jan. 1998

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Song Ben, Hong Wei. CAPACITANCE EXTRACTION OF THE VIA HOLE STRUCTURE EMBEDDED IN THE MULTILAYERED DIELECTRIC MEDIA[J]. Journal of Electronics & Information Technology, 1998, 20(1): 109-113.

Citation:

Song Ben, Hong Wei. CAPACITANCE EXTRACTION OF THE VIA HOLE STRUCTURE EMBEDDED IN THE MULTILAYERED DIELECTRIC MEDIA[J]. Journal of Electronics & Information Technology, 1998, 20(1): 109-113.

Song Ben, Hong Wei. CAPACITANCE EXTRACTION OF THE VIA HOLE STRUCTURE EMBEDDED IN THE MULTILAYERED DIELECTRIC MEDIA[J]. Journal of Electronics & Information Technology, 1998, 20(1): 109-113.

Citation:

Song Ben, Hong Wei. CAPACITANCE EXTRACTION OF THE VIA HOLE STRUCTURE EMBEDDED IN THE MULTILAYERED DIELECTRIC MEDIA[J]. Journal of Electronics & Information Technology, 1998, 20(1): 109-113.

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CAPACITANCE EXTRACTION OF THE VIA HOLE STRUCTURE EMBEDDED IN THE MULTILAYERED DIELECTRIC MEDIA

Song Ben,
Hong Wei

Received Date: 1996-04-24
Rev Recd Date: 1997-02-04
Publish Date: 1998-01-19

Abstract

Abstract

An efficient method to calculate the quasi-static capacitance of the via hole structure embedded in a multilayered dielectric media named Dimension Reduction Technique(DRT) is presented. Since the method takes full advantage of the characteristics of the stratified structure in integrated circuit, it can easily deal with the varied numbers of the dielectric layers as well as the varied structure parameters while only need little CPU time and memory space. The numerical results given in this paper are in good agreement with those of Ansofts software.

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References(1)

References

Wang T, Mautz J R, Harrington R F. The excess capacitance of a microstrip via in a dielectric substrate, IEEE Trans on CAD, 1990, CAD-9(1): 48-56.[2]Wang T, Harrington R, FMautz J R. Quasistatic analysis of a microstrip through a hole in ground plane, IEEE Trans. on MTT, 1988, MTT-36(6): 1008-1013.[3]KOP P, De Zutter D. Capacitance of a circular symmetric model of a via hole including finite ground plane thickness. IEEE Trans. on MTT, 1991, MTT-39(7): 1229-1234.[4]Mathis A W, Butler C M. Capacitance of circular symmetric via for microstrip transmission line, IEEE Proc. -H, 1994, 141(8): 265-271.[5]Faton Tefiku, Eidichi Yamashita. Efficient method for the capacitance calculation of circularly symmetric via in mutilayered media, IEEE Microwave and Guided Wave Letters, 1995, 5(9): 305-307.[6]Zhenhai Zhu, Wei Hong, et al. Electromagnetic modeling and transient simulation of interconnects in high speed VLSI, IEEE Multi-chip module conference MCMC 95, Santa Cruz, California: 1995.[7]朱震海,洪伟,陈忆元.集成电路中多导体传箱线的电磁参数提取和瞬态响应分析[J].电子学报.1996, 24(6):51-54[8]C Wei, Harrington R F, et al. Multiconductor transmission lines in multilayered dielectric media, IEEE Trans. on MTT, 1984, MTT-32(4): 439-450.

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