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Volume 28 Issue 3
Sep.  2010
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Chang Yi-feng, Yang Yin-tang. Study of Routing Algorithm in Multichip Modules[J]. Journal of Electronics & Information Technology, 2006, 28(3): 567-569.
Citation: Chang Yi-feng, Yang Yin-tang. Study of Routing Algorithm in Multichip Modules[J]. Journal of Electronics & Information Technology, 2006, 28(3): 567-569.

Study of Routing Algorithm in Multichip Modules

  • Received Date: 2005-02-03
  • Rev Recd Date: 2005-12-16
  • Publish Date: 2006-03-19
  • Aiming at the uneven routing results and much noise, this paper presents an improved method for multichip module routing that based on the four-via routing algorithm. By using the PST(Priority Search Tree) and LEA(Left Edge Algorithm) algorithms to restrict routing layers, remove vias or jogs and reduce noise, the result is optimized. The computer simulation results show that routing space is efficiently utilized and the delay and noise are also reduced in the field of electric feature.
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  • Wong C P, Wong M M. Recent advances in plastic packaging of flip-chip and MultiChip Modules(MCM) of microelectronics[J].IEEE Trans. on Components and Packaging Technology.1999, 22(1):21-25[2]Khoo Kei-Yong, Cong Jason. An efficient multilayer MCM router based on four-via routing. 30th ACM/IEEE Design Automation Conference. Santa Cruz, California, 1993: 590-595.[3]Khoo Kei-Yong, Cong Jason. A fast multilayer general area router for MCM designs[J].IEEE Trans. on Circuits and Systems.1992, 39(1):841-859[4]Yu Qiong.[J].Standeep B, Sherwani N. CD3D:A constraint-driven 3-dimensional router for MCMS. MCM98, California.1998,:-[5]Cong Jason, Madden P H. Performance driven multi-layer general area routing for PCB/MCM designs. Electronic Components and Technology Conference, Stockholm, Sweden, 1999: 356-361.[6]畅艺峰,杨银堂,柴常春. MCM高速电路布局布线设计及信号传输特性仿真. 西安电子科技大学学报,2005,32(1):44-47.[7]Dressel W, Mangold T. Time domain characterization of multichip module elements. IEEE Trans. on Microwave Theory and Techniques, 1998, 32(1): 1033-1036.[8]Pendurkar R Y. Design for testability techniques and optimization algorithms for performance and functional testing of multichip module interconnections. Abstracts International, 1999, Volume: 61-04, Section B: 2119.
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