Design of High-speed Asynchronous Pipeline Based on Parallel Completion Detection

A multi-threshold pipeline based on parallel completion is proposed to improve the throughput of asynchronous NULL Convention Logic (NCL) pipeline. With the special semi-static NCL threshold gates to be realized asynchronous combinational logic, data processing and completion detection of each pipeline stage are carried out parallelly, meanwhile, the data get through the pipeline by using serial mode. The series-parallel ways improve the throughput of the pipeline. Moreover, the static power of the pipeline in NULL cycle declines as well because of the new threshold gates. The proposed pipeline is simulated based on SMIC 0.18 m standard CMOS technology. Comparison results indicate that the throughput of the novel pipeline has an increment of 62.8% and the static power consumption is reduced by 40.5% with 4-bit NCL Ripper Adder serving as an asynchronous combinational logic. The proposed pipeline can be used to design high-speed low-power asynchronous circuit.