FPGA-based Joint Design of LDPC Encoder and Decoder

A joint design of FPGA-based encoder and decoder of LDPC codes is proposed. In this new design, the LDPC encoder and decoder share the same parity-check calculation circuit and the same RAM block, resulting in significantly reduced resource consumption in hardware implementations. The design is suitable for encoding and decoding realizations based on parity-check matrix. It can accommodate full-parallel architectures both for the encoder and decoder, or partial-parallel architectures that are widely adopted nowadays. Furthermore, various decoding algorithms such as the sum-product and the min-sum algorithms can be adopted in this design. The proposed joint design method is applied to design the enoder and decoder of two different groups of LDPC codes, both with a partial-parallel structure. The implementation based on an Xinlinx XC4VLX80 FPGA shows that the designed encoder and decoder can work well in a parallel way, and only consumes slightly more hardware resources than that required by a single decoder. As a result, the proposed design can effectively reduce the hardward consumption without sacrificing the throughput.