Research on Reliability Evaluation of Memories for Low-cost Fault Tolerant Design

Recent studies on soft errors focus on the low-cost fault tolerant techniques, thus motivating an early and accurate evaluation of microprocessor reliability (i.e., Architectural Vulnerability Factor (AVF)). However, current AVF evaluation tools have their own limitations in accuracy and applicability. In order to improve the accuracy of AVF estimation of the key structures of microprocessors (i.e., memories) for low-cost fault tolerant design, this paper proposes a Hybrid AVF Evaluation Strategy (HAES) which combines memory access analysis and instruction identification for AVF evaluation. Then the HAES is integrated into a general simulator and an improved AVF evaluation framework is implemented. Experimental results show that compared with other AVF evaluation tools, AVF computed using the evaluation framework is reduced by 22.6% averagely. AVFs which are estimated using the improved AVF evaluation framework reflect the reliability of memories more accurately, and play a significant role for low-cost fault tolerant design.