Deng Jun, Yang Yin-Tang. Structure of Interpolation Filter Based on Parallel Pipelining and Fast FIR Algorithm and Its Implementation for All Digital Receiver[J]. Journal of Electronics & Information Technology, 2010, 32(9): 2089-2094. doi: 10.3724/SP.J.1146.2009.01292
Citation:
Deng Jun, Yang Yin-Tang. Structure of Interpolation Filter Based on Parallel Pipelining and Fast FIR Algorithm and Its Implementation for All Digital Receiver[J]. Journal of Electronics & Information Technology, 2010, 32(9): 2089-2094. doi: 10.3724/SP.J.1146.2009.01292
Deng Jun, Yang Yin-Tang. Structure of Interpolation Filter Based on Parallel Pipelining and Fast FIR Algorithm and Its Implementation for All Digital Receiver[J]. Journal of Electronics & Information Technology, 2010, 32(9): 2089-2094. doi: 10.3724/SP.J.1146.2009.01292
Citation:
Deng Jun, Yang Yin-Tang. Structure of Interpolation Filter Based on Parallel Pipelining and Fast FIR Algorithm and Its Implementation for All Digital Receiver[J]. Journal of Electronics & Information Technology, 2010, 32(9): 2089-2094. doi: 10.3724/SP.J.1146.2009.01292
The analysis and research are based on the existing Farrow structure of Lagrange interpolation filter. The pipelining and parallel processing technology are used to improve the speed of filter. On this basis, a new structure based on the fast FIR algorithm is proposed. It is used to reduce the complexity of the parallel Farrow structure. The structure is implemented for FPGA. The analysis results show that the structure has faster operational rate and lower power consumption.
张公礼. 全数字接收机理论与技术[M]. 北京: 科学出版社, 2005年1月: 61-85.Zhang Gong-Li. Theory and Technology of All Digital Receiver[M]. Beijing: Science Press, 2005: 61-85.[2]Gardner F M. Interpolation in digital modems part I:fundamentals[J].IEEE Transactions on Communications.1993, 41(3):501-507[3]Erup L, Gardner F M, and Harris R A. Interpolation in digital modems part II: implementation and performance[J]. IEEE Transactions on Communications, 1993, 41(6): 1135-1141.[4]Merlino P and Abramo A. A fully pipelined architecture for the LOCO-I compression algorithm[J].IEEE Transactions on Very Large Scale Integration Systems.2009, 17(7):967-971[5]邓军, 杨银堂. 全数字接收机中一种低功耗插值滤波器结构及其VLSI实现[J]. 西安电子科技大学学报, 2010, 37(2): 320-325.Deng Jun and Yang Yin-tang. A structure of low-power interpolation filter and its VLSI implementation for all digital receiver[J]. Journal of Xidian University, 2010, 37(2): 320-325.[6]Tawfik S A and Ursun V K. Low power and high speed multi threshold voltage interface circuits[J].IEEE Transactions on Very Large Scale Integration Systems.2009, 17(5):638-645[7]Tam W P, Lok T M, and Wong T F. Flow optimization in parallel relay netwoks with cooperative relaying[J].IEEE Transactions on Wireless Communications.2009, 8(1):278-287[8]Polpo A and Pereira C A B. Reliability nonparametric Bayesian estimation in parallel system[J].IEEE Transactions on Reliability.2009, 58(2):364-373[9]Winograd S. Arithmetic complexity of computations. CBMS-NSF Regional Conference Series in Applied Mathematics, SIAM Publications, 1980, 33: 21-33.[10]Parker D A and Parhi K K. Low-area/power parallel FIR digital filter implementations[J]. Journal of VLSI Signal Processing, 1997, 2(1): 75-92.[11]Jain V and Blair W D. Filter design for steady-state tracking of maneuvering targets with LFM waveforms[J].IEEE Transactions on Aerospace and Electronic Systems.2009, 45(2):765-772