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Volume 32 Issue 6
Jun.  2010
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Qu Xiao-gang, Yang Hai-gang. Design Technique for Generating Large Delay in Area-Constraint Power-On Reset Circuit[J]. Journal of Electronics & Information Technology, 2010, 32(6): 1389-1394. doi: 10.3724/SP.J.1146.2009.00873
Citation: Qu Xiao-gang, Yang Hai-gang. Design Technique for Generating Large Delay in Area-Constraint Power-On Reset Circuit[J]. Journal of Electronics & Information Technology, 2010, 32(6): 1389-1394. doi: 10.3724/SP.J.1146.2009.00873

Design Technique for Generating Large Delay in Area-Constraint Power-On Reset Circuit

doi: 10.3724/SP.J.1146.2009.00873
  • Received Date: 2009-06-12
  • Rev Recd Date: 2009-09-18
  • Publish Date: 2010-06-19
  • To solve the problem of an excessive area required to implement milliseconds reset time with resistance and capacitance in POR (Power-On Reset) circuit, an area-efficiency delay circuit based on an exponential time-extending technique is proposed in this paper. The circuit utilizes asynchronous frequency division to increase delay exponentially, using the period of signal which ring oscillator generates as a reference delay unit and is capable of implementing milliseconds delay for minimum silicon area. It is used to generate a long enough reset time in the POR circuit. To verify the technique, the circuit is designed and fabricated in the SMIC 0.18 m process. According to the measured results, the circuit typically achieves 0.91 ms delay with an area of 172 m75 m and 54.9 ms delay with an area of 172 m95 m. As compared with RC method, the circuit can respectively save at least 82.8% and 97% layout area for implementing the same delays.
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  • Takeo Yasuda, Masaaki Yamamoto, and Takafumi Nishi. A power-on reset pulse generator for low voltage applications[C]. IEEE International Symposium on Circuits and Systems, Sydney, May 6-9, 2001, 4: 598-601.[2]Chen Kuo-Hsing and Lo Yu-Lung. A fast-lock DLL with power-on reset circuit[C]. Proc. International Symposium on Circuits and Systems, Vancouver, May 23-26, 2004, 4: 357-360.[3]McClintock C. Method and apparatus for creating a large delay in a pulse in a layout efficient manner[P]. US, No. 5606276, 1997.[4]Wadhwa S K, Siddhartha G K, and Gaurav A. Zero steady state current power-on-reset circuit with brown-out detector[C]. Proc. 19th International Conference on VLSI Design, Hyderabad, Jan. 3-7, 2006: 631-636.[5]Ker Ming-Dou, Yen Cheng-Cheng, and Shih Pi-Chia. On-chip transient detection circuit for system-level ESD protection in CMOS integrated circuits to meet electromagnetic compatibility regulation[J].IEEE Transactions on Electromagnetic Compatibility.2008, 50(1):13-21[6]Toru Tanzawa. A process- and temperature-tolerant power-on reset circuit with a flexible detection level higher than the bandgap voltage[C]. IEEE International Symposium on Circuits and Systems, Seattle, May 18-21, 2008: 2302-2305.[7]Yen Cheng-Cheng, Liao Chi-Sheng, and Ker Ming-Dou. New transient detection circuit for system-level ESD protection[C]. IEEE International Symposium on VLSI Design, Automation and Test, Hsinchu, April 23-25, 2008: 180-183.[8]Choi W B. Power-on reset circuit[P]. U S, No. 20080100351, 2008.[9]Lai Xin-quan, Yu Wei-xue, and Li Gang, et al.. A low quiescent current and reset time adjustable power-on reset circuit[C]. 6th International Conference on ASIC, Shanghai, Oct. 2005, 2: 559-562.
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