Design Technique for Generating Large Delay in Area-Constraint Power-On Reset Circuit

Qu Xiao-gang; Yang Hai-gang

doi:10.3724/SP.J.1146.2009.00873

Volume 32 Issue 6

Jun. 2010

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Article Navigation > Journal of Electronics & Information Technology > 2010 > 32(6): 1389-1394

Qu Xiao-gang, Yang Hai-gang. Design Technique for Generating Large Delay in Area-Constraint Power-On Reset Circuit[J]. Journal of Electronics & Information Technology, 2010, 32(6): 1389-1394. doi: 10.3724/SP.J.1146.2009.00873

Citation:

Qu Xiao-gang, Yang Hai-gang. Design Technique for Generating Large Delay in Area-Constraint Power-On Reset Circuit[J]. Journal of Electronics & Information Technology, 2010, 32(6): 1389-1394. doi: 10.3724/SP.J.1146.2009.00873

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Design Technique for Generating Large Delay in Area-Constraint Power-On Reset Circuit

doi: 10.3724/SP.J.1146.2009.00873

Qu Xiao-gang^{①②;杨海钢},
Yang Hai-gang

Received Date: 2009-06-12
Rev Recd Date: 2009-09-18
Publish Date: 2010-06-19

Abstract

Abstract

To solve the problem of an excessive area required to implement milliseconds reset time with resistance and capacitance in POR (Power-On Reset) circuit, an area-efficiency delay circuit based on an exponential time-extending technique is proposed in this paper. The circuit utilizes asynchronous frequency division to increase delay exponentially, using the period of signal which ring oscillator generates as a reference delay unit and is capable of implementing milliseconds delay for minimum silicon area. It is used to generate a long enough reset time in the POR circuit. To verify the technique, the circuit is designed and fabricated in the SMIC 0.18 m process. According to the measured results, the circuit typically achieves 0.91 ms delay with an area of 172 m75 m and 54.9 ms delay with an area of 172 m95 m. As compared with RC method, the circuit can respectively save at least 82.8% and 97% layout area for implementing the same delays.

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References(1)

References

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