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Volume 32 Issue 7
Aug.  2010
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Yu Yun-feng, Ma Cheng-yan, Ye Tian-chun. A New Low-Power High-Speed Prescaler in GNSS Receivers[J]. Journal of Electronics & Information Technology, 2010, 32(7): 1752-1755. doi: 10.3724/SP.J.1146.2009.00842
Citation: Yu Yun-feng, Ma Cheng-yan, Ye Tian-chun. A New Low-Power High-Speed Prescaler in GNSS Receivers[J]. Journal of Electronics & Information Technology, 2010, 32(7): 1752-1755. doi: 10.3724/SP.J.1146.2009.00842

A New Low-Power High-Speed Prescaler in GNSS Receivers

doi: 10.3724/SP.J.1146.2009.00842
  • Received Date: 2009-06-03
  • Rev Recd Date: 2010-01-18
  • Publish Date: 2010-07-19
  • A new prescaler based on new Source Coupled Logic(SCL) latch is proposed in this paper, supplying Local Oscillator (LO) for receivers. Compared to traditional static SCL latch, a clock-controlling transistor is added to reduce the time constant at sensing time, and as a result, the maximum operating frequency increases and the operating range is enlarged. A simple but to some extent accurate small signal model for this new architecture is developed, and the advantages of new design are described in detail. This prescalers maximum operating frequency can reach to 6.9 GHz when its current is only 1.2 mA. The prescaler is manufactured in 0.18 m CMOS process, and it has been successfully applied to GPS receivers.
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