High-Speed Hardware Implementation for GCM in IEEE802.1AE

This paper presents a high-speed GCM architecture, which is suitable for IEEE 802.1AE protocol. The core modules of GCM include AES and Ghash. In Ghash module, a new parallel multiply-adder is proposed, which can handle several sets of data at the same time without knowing the total number of data blocks in advance. To support constant key changes in each clock cycle, loop-unrolling structure is used in KeyExpansion module of AES. A GCM encryptor design example with 2-parallel Ghash is implemented and the performance is evaluated by utilizing Fujitsu 0.13 m 1.2 V 1P8M CMOS technology and a very high throughput of 97.9 Gbps is obtained with 547 Kgates, operating at 764.5 MHz.