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Volume 32 Issue 6
Jun.  2010
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Cui Xiu-hai, Yang Hai-gang, Gong Xiao, Huang Juan, Tan Yi-tao. A Research on Subsection Progressive Optimization Placement Algorithm of FPGA[J]. Journal of Electronics & Information Technology, 2010, 32(6): 1395-1400. doi: 10.3724/SP.J.1146.2008.01689
Citation: Cui Xiu-hai, Yang Hai-gang, Gong Xiao, Huang Juan, Tan Yi-tao. A Research on Subsection Progressive Optimization Placement Algorithm of FPGA[J]. Journal of Electronics & Information Technology, 2010, 32(6): 1395-1400. doi: 10.3724/SP.J.1146.2008.01689

A Research on Subsection Progressive Optimization Placement Algorithm of FPGA

doi: 10.3724/SP.J.1146.2008.01689
  • Received Date: 2008-12-12
  • Rev Recd Date: 2010-04-20
  • Publish Date: 2010-06-19
  • A novel FPGA simulated annealing placement algorithm is proposed to improve the routability and optimize the length of wires. Different cost functions are applied to different temperature range. In high temperature stage, the half perimeter method is utilized to fast optimize the placement; while in low temperature stage, a variable factor is added into the cost function and the reasonable temper process is also used to improve the quality of placement. Experiment results demonstrate that, compared with the VPR, the proposed method requires 6% fewer routing tracks and the length of wire is 4~23% shorter.
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