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Volume 29 Issue 2
Jan.  2011
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Wang Jian-xin, Yu Gui-zhi. Study on Implementation of Traceback Algorithm in Viterbi Decoders[J]. Journal of Electronics & Information Technology, 2007, 29(2): 278-282. doi: 10.3724/SP.J.1146.2005.00614
Citation: Wang Jian-xin, Yu Gui-zhi. Study on Implementation of Traceback Algorithm in Viterbi Decoders[J]. Journal of Electronics & Information Technology, 2007, 29(2): 278-282. doi: 10.3724/SP.J.1146.2005.00614

Study on Implementation of Traceback Algorithm in Viterbi Decoders

doi: 10.3724/SP.J.1146.2005.00614
  • Received Date: 2005-05-30
  • Rev Recd Date: 2006-03-20
  • Publish Date: 2007-02-19
  • This paper discusses two traceback algorithms for Viterbi decoder. The realization methods for the traceback algorithms with FPGA are given through optimization for the hardware architecture. The comparison between the two realization methods is given. Finally, the two realization methods are applied to Viterbi decoder, and both simulation and hardware test show that the presented implementation methods are correct.
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  • [1] Viterbi A J. Error bounds for convolutional codes and an asymptotically optimum decoding algorithm [J].IEEE Trans. on Information Theory.1967, 13(2):260-269 [2] Rader C M. Memory management in a Vitrbi decoder [J].IEEE Trans. on Communications.1981, 29(9):1399-1401 [3] Feygin G and Gulak P G. Architectural tradeoffs for survivor sequence memory management in Viterbi decoders [J].IEEE Trans. on Communications.1993, 41(3):425-429 [4] Black P J and Meng T H. A 140-Mb/s, 32-state, radix-4 Viterbi decoder [J].IEEE Journal of Solid-State Circuits.1992, 27(12):1877-1885 [5] Corporation A. Cyclone Device Handbook, Volume 1 [M]. 2003.
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