A System-level Exploration and Evaluation Simulator for chiplet-based CPU

ZHANG Congwu; LIU Ao; ZHANG Ke; CHANG Yisong; BAO Yungang

doi:10.11999/JEIT240299

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ZHANG Congwu, LIU Ao, ZHANG Ke, CHANG Yisong, BAO Yungang. A System-level Exploration and Evaluation Simulator for chiplet-based CPU[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT240299

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ZHANG Congwu, LIU Ao, ZHANG Ke, CHANG Yisong, BAO Yungang. A System-level Exploration and Evaluation Simulator for chiplet-based CPU[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT240299

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A System-level Exploration and Evaluation Simulator for chiplet-based CPU

doi: 10.11999/JEIT240299

ZHANG Congwu^{1, 2},
LIU Ao^{1, 3},
ZHANG Ke^{1, 2
,
,},
CHANG Yisong^{1, 2},
BAO Yungang^{1, 2}

1.
State Key Lab of Processors (Institute of Computing Technology, Chinese Academy of Sciences), Beijing 100190, China
2.
School of Computer Science and Technology, University of Chinese Academy of Sciences, Beijing 100049, China
3.
Henan Institute of Advanced Technology, Zhengzhou University, Zhengzhou 450003, China

Funds: The Strategic Priority Research Program of Chinese Academy of Sciences (XDA0320000, XDA0320300), The MajorProgram of the National Natural Science Foundation of China (62090020)

Received Date: 2024-04-19
Rev Recd Date: 2024-11-11

Available Online: 2024-11-19

Abstract

Abstract

As Moore’s Law comes to an end, it is more and more difficult to improve the chip manufacturing process, and chiplet technology has been widely adopted to improve the chip performance. However, new design parameters introduced into the chiplet architecture pose significant challenges to the computer architecture simulator. To fully support exploration and evaluation of chiplet architecture, SEEChiplet (System-level Exploration and Evaluation simulator for chiplet), a framework based on gem5 simulator, is developed in this paper. Firstly, three design parameters concerned about chiplet chip design are summarized in this paper, including: (1) chiplet cache system design; (2) Packaging simulation; (3) Interconnection networks between chiplet. Secondly, in view of the above three design parameters, in this paper: (1) a new private last level cache system are designed and implemented to expand the cache system design space; (2) existing gem5 global directory is modified to adapt to new private Last Level cache (LLC) system; (3) two common packaging methods of chiplet and inter-chiplet network are modeled. Finally, a chiplet-based processor is simulated with PARSEC 3.0 benchmark program running on it, which proves that SEEChiplet can explore and evaluate the design space of chiplet.
- Chiplet,
- Design space exploration,
- Computer architecture simulator,
- Cache system

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References(42)

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