SDL PUF: A High Reliability Self-Adaption Deviation Locking PUF

ZHANG Yuan; LUO Jingru; ZHANG Jiliang

doi:10.11999/JEIT231313

Volume 46 Issue 5

May 2024

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Article Navigation > Journal of Electronics & Information Technology > 2024 > 46(5): 2274-2280

ZHANG Yuan, LUO Jingru, ZHANG Jiliang. SDL PUF: A High Reliability Self-Adaption Deviation Locking PUF[J]. Journal of Electronics & Information Technology, 2024, 46(5): 2274-2280. doi: 10.11999/JEIT231313

Citation:

ZHANG Yuan, LUO Jingru, ZHANG Jiliang. SDL PUF: A High Reliability Self-Adaption Deviation Locking PUF[J]. Journal of Electronics & Information Technology, 2024, 46(5): 2274-2280. doi: 10.11999/JEIT231313

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SDL PUF: A High Reliability Self-Adaption Deviation Locking PUF

doi: 10.11999/JEIT231313

College of Semiconductors (College of Integrated Circuits), Hunan University, Changsha 410000, China

Funds: The National Natural Science Foundation of China(U20A20202, 62122023)

Received Date: 2023-11-29
Rev Recd Date: 2024-05-21

Available Online: 2024-05-23

Publish Date: 2024-05-30

Abstract

Abstract

As a novel hardware security primitive, Physical Unclonable Function (PUF) extracts process deviations to generate a unique response sequence, providing a root of trust for computing systems. However, existing PUFs based on Field Programmable Gate Arrays (FPGAs) cannot maintain high reliability over a wide range of temperatures and voltages. In this work, we propose a Self-Timed Ring (STR) based Self-adaption Deviation Locking PUF (SDL PUF). Firstly, the PUF response is generated utilizing the oscillation frequency difference caused by the STR delay. Secondly, the adaptive configuration in the initialization stage can effectively expand the deviation of the event arrival time in the STR, substantially enhancing the reliability of PUF. Finally, a comparator obfuscation strategy is proposed, automatically configuring the comparator by extracting the process deviation to resist the side-channel attack. The proposed structure is implemented on a Xilinx Virtex-6 FPGA. Experimental results show that the proposed SDL PUF achieves 0 bit error rate in the temperature range of 0°C～80°C and the voltage range of 0.85～1.15V, and ensures 49.29% uniqueness and 49.84% uniformity while maintaining high reliability.
- Physical unclonable function,
- Self-timed ring,
- FPGA,
- Reliability

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References(22)

References

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