Cost-Effective TMR Soft Error Tolerance Technique for Commercial Aerospace: Utilization of Approximate Computing

LI Yan; HU Yueming; ZENG Xiaoyang

doi:10.11999/JEIT231288

Volume 46 Issue 5

May 2024

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Article Navigation > Journal of Electronics & Information Technology > 2024 > 46(5): 1604-1612

LI Yan, HU Yueming, ZENG Xiaoyang. Cost-Effective TMR Soft Error Tolerance Technique for Commercial Aerospace: Utilization of Approximate Computing[J]. Journal of Electronics & Information Technology, 2024, 46(5): 1604-1612. doi: 10.11999/JEIT231288

Citation:

LI Yan, HU Yueming, ZENG Xiaoyang. Cost-Effective TMR Soft Error Tolerance Technique for Commercial Aerospace: Utilization of Approximate Computing[J]. Journal of Electronics & Information Technology, 2024, 46(5): 1604-1612. doi: 10.11999/JEIT231288

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Cost-Effective TMR Soft Error Tolerance Technique for Commercial Aerospace: Utilization of Approximate Computing

doi: 10.11999/JEIT231288

Fudan University State Key Laboratory of Integrated Chips and Systems, Shanghai 201203, China

Funds: The National Natural Science Foundation of China (62204045), Shanghai Pujiang Program (22PJD005)

Received Date: 2023-11-21
Rev Recd Date: 2024-04-08

Available Online: 2024-05-07

Publish Date: 2024-05-30

Abstract

Abstract

Triple Modular Redundancy (TMR), as the most prevalent and effective technique for soft error mitigation technique, inevitably incurs substantial hardware overhead while meeting high fault-tolerance requirements. To achieve the trade-off between area, power and fault coverage and meet the requirement of low-cost and high-reliability circuit design, Approximate Triple Modular Redundancy (ATMR) is investigated and a Dynamic Adjustment Multi-Objective Optimization Framework based on Approximate Gate Library (ApxLib+DAMOO) is investigated. The basic optimization framework employs Non-dominated Sorting Genetic Algorithm II (NSGA-II), achieving rapidly approximation through parity analysis and the pre-established ApxLib. Subsequently, the framework introduces two novel mechanisms: dynamic probability adjustment and parity expansion. The first mechanism dynamically updates the mutation probability of gates in the genetic algorithm based on testability analysis, while the second mechanism performs recognition and reconstruction for binate gates to achieve dual optimization of efficiency and effectiveness in optimization. Experimental results indicate that the proposed optimization framework achieves an additional Soft Error Rate (SER) reduction of up to 10%～20% compared to traditional NSGA-II with the same hardware overhead, while reducing 18.7% of execution time reduction averagely.
- Soft error tolerance,
- Triple modular redundancy,
- Approximate computing,
- Multi-objective optimization

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References(19)

References

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