A Low-Power Network-on-Chip Power-Gating Design with Bypass Mechanism

OUYANG Yiming; CHEN Zhiyuan; XÜ Dongyu; LIANG Huaguo

doi:10.11999/JEIT231257

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OUYANG Yiming, CHEN Zhiyuan, XÜ Dongyu, LIANG Huaguo. A Low-Power Network-on-Chip Power-Gating Design with Bypass Mechanism[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT231257

Citation:

OUYANG Yiming, CHEN Zhiyuan, XÜ Dongyu, LIANG Huaguo. A Low-Power Network-on-Chip Power-Gating Design with Bypass Mechanism[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT231257

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A Low-Power Network-on-Chip Power-Gating Design with Bypass Mechanism

doi: 10.11999/JEIT231257

School of Computing and Information, Hefei University of Technology, Hefei 230601, China

Funds: The National Natural Science Foundation of China (62374049)

Received Date: 2023-11-14
Rev Recd Date: 2024-04-23

Available Online: 2024-05-13

Abstract

Abstract

Static power consumption dominates the power overhead of Network-on-Chip (NoC) as the technology size shrinks. Power gating, a generalized power saving technique, turns off idle modules in NoCs to reduce static power consumption. However, the conventional power gating technique brings problems such as packet wake-up delay, break-even time, etc. To solve the above problems, Partition Bypass Transmission Infrastructure (PBTI) is proposed in the paper, being adopted for packet transmission in place of a power-gated router, and a low-latency, low-power power gating scheme has been designed based upon this bypass mechanism. PBTI uses mutually independent bypasses to process separately the PBTI uses independent bypasses to handle east-west packets separately, and uses common buffers within the bypasses to improve buffer utilization. PBTI can inject, transmit, and eject packets when the router is powered off. Packets can be transmitted from the source node to the destination node even if all routers in the network are power gated. When the traffic increases beyond the transmission capacity of PBTI, the routers perform a uniform wake-up in columns. Experimental results show that compared to the NoC without power gating, the scheme in this paper reduces 83.4% of static power consumption and 17.2% of packet delay, while adding only 6.2% additional area overhead. Compared to the conventional power gating scheme the power gated design in this paper achieves lower power consumption and delay, which is a significant advantage.
- Network-on-Chip,
- Power gating,
- Bypass,
- Static power

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References(15)

References

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