Citation: | NI Tianming, YU Junyong, PENG Qingsong, NIE Mu. Design of High Throughput True Random Number Generator Based on Metastability Superposition Cells[J]. Journal of Electronics & Information Technology, 2024, 46(5): 2289-2297. doi: 10.11999/JEIT231166 |
[1] |
CORRIGAN-GIBBS H, MU W, BONEH D, et al. Ensuring high-quality randomness in cryptographic key generation[C]. 2013 ACM SIGSAC Conference on Computer & Communications Security, Berlin, Germany, 2013: 685–696. doi: 10.1145/2508859.2516680.
|
[2] |
CHAKRABORTY S, GARG A, and SURI M. True random number generation from commodity NVM chips[J]. IEEE Transactions on Electron Devices, 2020, 67(3): 888–894. doi: 10.1109/TED.2019.2963203.
|
[3] |
YANG Bohan, ROŽIC V, GRUJIC M, et al. ES-TRNG: A high-throughput, low-area true random number generator based on edge sampling[J]. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2018, 2018(3): 267–292. doi: 10.13154/tches.v2018.i3.267-292.
|
[4] |
TANG Qianying, KIM B, LAO Yingjie, et al. True random number generator circuits based on single- and multi-phase beat frequency detection[C]. IEEE 2014 Custom Integrated Circuits Conference, San Jose, USA, 2014: 1–4. doi: 10.1109/CICC.2014.6946136.
|
[5] |
ROBOSON S, LEUNG B, and GONG G. Truly random number generator based on a ring oscillator utilizing last passage time[J]. IEEE Transactions on Circuits and Systems II:Express Briefs, 2014, 61(12): 937–941. doi: 10.1109/TCSII.2014.2362715.
|
[6] |
KWOK S H M and LAM E Y. FPGA-based high-speed true random number generator for cryptographic applications[C]. 2006 IEEE Region 10 Conference, Hong Kong, China, 2006: 1–4. doi: 10.1109/TENCON.2006.344013.
|
[7] |
FISCHER V, DRUTAROVSKÝ M, ŠIMKA M, et al. High performance true random number generator in Altera stratix FPLDs[C]. 14th International Conference and Field Programmable Logic and Application, Leuven, Belgium, 2004: 555–564. doi: 10.1007/978-3-540-30117-2_57.
|
[8] |
MEITEI H B and KUMAR M. FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter[J]. SN Applied Sciences, 2022, 4(4): 96. doi: 10.1007/s42452-022-04981-6.
|
[9] |
LIN Jianming, WANG Yonggang, ZHAO Zelong, et al. A new method of true random number generation based on Galois ring oscillator with event sampling architecture in FPGA[C]. 2020 IEEE International Instrumentation and Measurement Technology Conference, Dubrovnik, Croatia, 2020: 1–6. doi: 10.1109/I2MTC43012.2020.9129357.
|
[10] |
GOLIC J D J. New methods for digital generation and postprocessing of random data[J]. IEEE Transactions on Computers, 2006, 55(10): 1217–1229. doi: 10.1109/TC.2006.164.
|
[11] |
DICHTL M. Fibonacci ring oscillators as true random number generators—a security risk[J]. IACR Cryptology ePrint Archive, 2015, 2015: 270.
|
[12] |
WANG Xinyu, LIANG Huaguo, WANG Yanjie, et al. High-throughput portable true random number generator based on jitter-latch structure[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2021, 68(2): 741–750. doi: 10.1109/TCSI.2020.3037173.
|
[13] |
GU Haoang, DENG Fangyu, WANG Qin, et al. A four-phase self-timed ring based true random number generator on FPGA[C]. 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), Nangjing, China, 2022: 1–3. doi: 10.1109/ICSICT55466.2022.9963322.
|
[14] |
CUI Jianguo, YI Maoxiang, CAO Di, et al. Design of true random number generator based on multi-stage feedback ring oscillator[J]. IEEE Transactions on Circuits and Systems II:Express Briefs, 2022, 69(3): 1752–1756. doi: 10.1109/TCSII.2021.3111049.
|
[15] |
PARK J, KIM B, and SIM J Y. A PVT-tolerant oscillation-collapse-based true random number generator with an odd number of inverter stages[J]. IEEE Transactions on Circuits and Systems II:Express Briefs, 2022, 69(10): 4058–4062. doi: 10.1109/TCSII.2022.3184950.
|
[16] |
GRUJIĆ M and VERBAUWHEDE I. TROT: A three-edge ring oscillator based true random number generator with time-to-digital conversion[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(6): 2435–2448. doi: 10.1109/TCSI.2022.3158022.
|
[17] |
DI PATRIZIO STANCHIERI G, DE MARCELLIS A, PALANGE E, et al. A true random number generator architecture based on a reduced number of FPGA primitives[J]. AEU - International Journal of Electronics and Communications, 2019, 105: 15–23. doi: 10.1016/j.aeue.2019.03.006.
|
[18] |
MAJZOOBI M, KOUSHANFAR F, and DEVADAS S. FPGA-based true random number generation using circuit metastability with adaptive feedback control[C]. 13th International Workshop on Cryptographic Hardware and Embedded Systems, Nara, Japan, 2011: 17–32. doi: 10.1007/978-3-642-23951-9_2.
|
[19] |
FRUSTACI F, SPAGNOLO F, PERRI S, et al. A high-speed FPGA-based true random number generator using metastability with clock managers[J]. IEEE Transactions on Circuits and Systems II:Express Briefs, 2023, 70(2): 756–760. doi: 10.1109/TCSII.2022.3211278.
|
[20] |
WIECZOREK P Z. Dual-metastability FPGA-based true random number generator[J]. Electronics Letters, 2013, 49(12): 744–745. doi: 10.1049/el.2012.4126.
|
[21] |
VON NEUMANN J. Various techniques used in connection with random digits[J]. National Bureau of Standards Applied Mathematics Series, 1951, 12: 36–38.
|
[22] |
WIECZOREK P Z. An FPGA implementation of the resolve time-based true random number generator with quality control[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2014, 61(12): 3450–3459. doi: 10.1109/TCSI.2014.2338615.
|
[23] |
JIN Liyu, YI Maoxiang, XIAO Yuan, et al. A dynamically reconfigurable entropy source circuit for high-throughput true random number generator[J]. Microelectronics Journal, 2023, 133: 105690. doi: 10.1016/j.mejo.2023.105690.
|
[24] |
WIECZOREK P Z. Lightweight TRNG based on multiphase timing of bistables[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2016, 63(7): 1043–1054. doi: 10.1109/tcsi.2016.2555248.
|
[25] |
DELLA SALA R, BELLIZIA D, and SCOTTI G. High-throughput FPGA-compatible TRNG architecture exploiting multistimuli metastable cells[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2022, 69(12): 4886–4897. doi: 10.1109/TCSI.2022.3199218.
|
[26] |
MEI Faqiang, ZHANG Lei, GU Chongyan, et al. A highly flexible lightweight and high speed true random number generator on FPGA[C]. 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China, 2018: 399–404. doi: 10.1109/ISVLSI.2018.00079.
|