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Volume 46 Issue 5
May  2024
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YU Hong, LIU Qinrang, WEI Shuai, LAN Julong. Executer Synchronization in Highly Reliable Information System with Dissimilar Redundancy Architecture[J]. Journal of Electronics & Information Technology, 2024, 46(5): 2122-2136. doi: 10.11999/JEIT231048
Citation: YU Hong, LIU Qinrang, WEI Shuai, LAN Julong. Executer Synchronization in Highly Reliable Information System with Dissimilar Redundancy Architecture[J]. Journal of Electronics & Information Technology, 2024, 46(5): 2122-2136. doi: 10.11999/JEIT231048

Executer Synchronization in Highly Reliable Information System with Dissimilar Redundancy Architecture

doi: 10.11999/JEIT231048
Funds:  The National Key R&D Program of China (2022YFB4401401)
  • Received Date: 2023-09-27
  • Rev Recd Date: 2024-03-16
  • Available Online: 2024-04-03
  • Publish Date: 2024-05-30
  • Dissimilar redundancy architecture is widely used in information systems to improve their security and reliability. When the system operates normally, the executers behave consistently, but when faced with malicious attacks, the executers exhibit inconsistency. The architecture improves the security and reliability of the system by comparing the performance of the executers to monitor the system and perceive threats. The synchronization of executers is a challenge that all dissimilar redundancy architectures need to address. There is currently no systematic description and summary of synchronization technology. This article is a review of executer synchronization techniques in dissimilar redundancy architectures. First, the importance of synchronization in dissimilar redundancy systems is explained and a standardized description of synchronization is provided. Then, a synchronization technology classification method based on synchronization points is proposed and the basic process, popularity, advantages and disadvantages of each class are summarized separately. This article also proposes three important indicators that affect synchronization performance, namely synchronization point, false alarm rate, and performance, and provides a mathematical model for synchronization technology, which can be used for design evaluation. Finally, this article combines the development of cyber resilience and software defined system on wafer, and points out the potential and possible directions for the future development of synchronous technology.
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