Critical Gates Localization of Logic Circuits Based on Correlation Separation

CAI Shuo; HE Huihuang; YU Fei; YIN Lairong; LIU Yang

doi:10.11999/JEIT230012

Volume 46 Issue 1

Jan. 2024

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Article Navigation > Journal of Electronics & Information Technology > 2024 > 46(1): 362-372

CAI Shuo, HE Huihuang, YU Fei, YIN Lairong, LIU Yang. Critical Gates Localization of Logic Circuits Based on Correlation Separation[J]. Journal of Electronics & Information Technology, 2024, 46(1): 362-372. doi: 10.11999/JEIT230012

Citation:

CAI Shuo, HE Huihuang, YU Fei, YIN Lairong, LIU Yang. Critical Gates Localization of Logic Circuits Based on Correlation Separation[J]. Journal of Electronics & Information Technology, 2024, 46(1): 362-372. doi: 10.11999/JEIT230012

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Critical Gates Localization of Logic Circuits Based on Correlation Separation

doi: 10.11999/JEIT230012

1.
School of Computer and Communication Engineering, Changsha University of Science and Technology, Changsha 410114, China
2.
College of Automotive and Mechanical Engineering, Changsha University of Science and Technology, Changsha 410114, China
3.
Zhongtong Service Consulting Design and Research Institute Company Limited, Nanjing 210019, China

Funds: The National Natural Science Foundation of China (62172058), The Natural Science Foundation of Hunan Province (2022JJ10052, 2022JJ30624)

Received Date: 2023-01-10
Rev Recd Date: 2023-04-12

Available Online: 2023-04-20

Publish Date: 2024-01-17

Abstract

Abstract

With the feature size of CMOS device entering the nanoscale, the circuit failure issue caused by high-energy particle radiation is becoming more and more serious, which brings severe challenges to the circuit reliability. At present, it is urgent to accurately evaluate the reliability of the integrated circuit and reinforce the fault tolerance of circuit, so as to improve the reliability of the circuit system. However, due to the large number of fan-out reconvergence structures in the logic circuit, the resulting signal correlation causes difficulties in reliability evaluation and critical gates location. This paper proposes critical gates location algorithm for logic circuit based on correlation separation. First, the circuit is divided into multiple Independent Circuit Structures (ICS); second, taking ICS as the basic unit to analyze fault propagation and signal correlation; Then, the circuit module after correlation separation and the reverse search algorithm is used to accurately locate the circuit critical gates; Finally, critical gates location and targeted fault tolerance reinforcement for the input vector space are comprehensively considered. The experimental results show that proposed algorithm can accurately and efficiently locate the critical gates of logic circuit, and it is suitable for reliability evaluation and efficient fault-tolerant design of large-scale and super-scale circuits.
- Logic circuit,
- Failure,
- Correlation separation,
- Critical gate location,
- Fault tolerant design

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References(20)

References

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