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Volume 45 Issue 1
Jan.  2023
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YAO Liang, LIANG Huaguo, YANG Shihao, ZHANG Hong, LU Yingchun. Research on Highly Portable Lightweight Physical Unclonable Functions Using Multiplexer Entropy Sources[J]. Journal of Electronics & Information Technology, 2023, 45(1): 68-77. doi: 10.11999/JEIT221263
Citation: YAO Liang, LIANG Huaguo, YANG Shihao, ZHANG Hong, LU Yingchun. Research on Highly Portable Lightweight Physical Unclonable Functions Using Multiplexer Entropy Sources[J]. Journal of Electronics & Information Technology, 2023, 45(1): 68-77. doi: 10.11999/JEIT221263

Research on Highly Portable Lightweight Physical Unclonable Functions Using Multiplexer Entropy Sources

doi: 10.11999/JEIT221263
Funds:  The National Natural Science Foundation of China (62174048)
  • Received Date: 2022-09-30
  • Rev Recd Date: 2022-12-21
  • Available Online: 2022-12-23
  • Publish Date: 2023-01-17
  • SR Latches Physical Unclonable Functions (PUFs) are the most popular FPGA-based cryptographic applications and have a broad market in lightweight IoT devices. To realize a symmetric unbiased SR latch PUF, different implementation methods that increase area consumption have been proposed. In this paper, a novel MUX-unit-based delay gate is proposed to form the M_SR PUF unit, and the output of the SR latch in the steady state is extracted as the response of the PUF. To verify the proposed M_SR PUF, it is implemented on three series of FPGAs from Xilinx Virtex-6, Virtex-7 and Kintex-7. It is worth mentioning that the symmetrical layout is relatively simple to implement through “hard macros”, which ensures better performance of PUF. The experimental results show that the proposed M_SR PUF can work stably under an ultra-wide range of environmental changes (temperature: 0°C ~80 °C; voltage: 0.8~1.2 V) with an average uniqueness of 50.125%. Furthermore, the proposed M_SR PUF unit is characterized by low overhead, consuming only 4 MUXs and 2 DFFs, and produces a high-entropy response suitable for hardware security applications.
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  • [1]
    SUNAR B, MARTIN W J, and STINSON D R. A provably secure true random number generator with built-in tolerance to active attacks[J]. IEEE Transactions on Computers, 2007, 56(1): 109–119. doi: 10.1109/TC.2007.250627
    [2]
    TANEJA S, RAJANNA V K, and ALIOTO M. 36.1 Unified in-memory dynamic TRNG and multi-bit static PUF entropy generation for ubiquitous hardware security[C]. Proceedings of 2021 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, 2021: 498–500.
    [3]
    SURAGANI R, NAZARENKO E, ANAGNOSTOPOULOS N A, et al. Identification and classification of corrupted PUF responses via machine learning[C]. Proceedings of 2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), McLean, USA, 2022: 137–140.
    [4]
    KROEGER T, CHENG Wei, GUILLEY S, et al. Cross-PUF attacks on arbiter-PUFs through their power side-channel[C]. Proceedings of 2020 IEEE International Test Conference (ITC), Washington, USA, 2020: 1–5.
    [5]
    CHANG Zhengtai, SHI Shanshan, SONG Binwei, et al. Modeling attack resistant arbiter PUF with time-variant obfuscation scheme[C]. Proceedings of 2021 31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 2021: 60–63.
    [6]
    YAO Liang, LIANG Huaguo, HAN Qian, et al. M-RO PUF: A portable pure digital RO PUF based on MUX unit[J]. Microelectronics Journal, 2022, 119: 105314. doi: 10.1016/j.mejo.2021.105314
    [7]
    OKUMURA S, YOSHIMOTO S, KAWAGUCHI H, et al. A 128-bit chip identification generating scheme exploiting load transistors' variation in SRAM bitcells[J]. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2012, E95.A(12): 2226–2233. doi: 10.1587/transfun.E95.A.2226
    [8]
    ARDAKANI A and SHOKOUHI S B. A secure and area-efficient FPGA-based SR-Latch PUF[C]. Proceedings of 2016 8th International Symposium on Telecommunications (IST), Tehran, Iran, 2016: 94–99.
    [9]
    YAMAMOTO D, SAKIYAMA K, IWAMOTO M, et al. Uniqueness enhancement of PUF responses based on the locations of random outputting RS latches[C]. Proceedings of the 13th International Workshop on Cryptographic Hardware and Embedded Systems, Nara, Japan, 2011: 390–496.
    [10]
    DANGER J L, YASHIRO R, GRABA T, et al. Analysis of mixed PUF-TRNG circuit based on SR-latches in FD-SOI technology[C]. Proceedings of the 21st Euromicro Conference on Digital System Design (DSD), Prague, Czech Republic, 2018: 508–515.
    [11]
    XU Xiumin, LIANG Huaguo, HUANG Zhengfeng, et al. A highly reliable butterfly PUF in SRAM-based FPGAs[J]. IEICE Electronics Express, 2017, 14(14): 20170551. doi: 10.1587/elex.14.20170551
    [12]
    LOTFY A, KAVEH M, MARTÍN D, et al. An efficient design of anderson PUF by utilization of the xilinx primitives in the SLICEM[J]. IEEE Access, 2021, 9: 23025–23034. doi: 10.1109/ACCESS.2021.3056291
    [13]
    NOZAKI Y, TAKEMOTO S, IKEZAKI Y, et al. Performance evaluation of unrolled cipher based glitch PUF implemented on virtex-7[C]. Proceedings of 2021 International Symposium on Devices, Circuits and Systems (ISDCS), Higashihiroshima, Japan, 2021: 1–4.
    [14]
    ZHOU Kai, LIANG Huaguo, JIANG Yue, et al. FPGA-based RO PUF with low overhead and high stability[J]. Electronics Letters, 2019, 55(9): 510–513. doi: 10.1049/el.2019.0451
    [15]
    CUI Yijun, CHEN Yunpeng, WANG Chenghua, et al. Programmable ring oscillator PUF based on switch matrix[C]. Proceedings of 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020: 1–4.
    [16]
    ZHOU Ting, JI Yuxin, CHEN Mingyi, et al. PL-MRO PUF: High speed pseudo-LFSR PUF based on multiple ring oscillators[C]. Proceedings of 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020: 1–5.
    [17]
    YAO Liang, LIANG Huaguo, HUANG Zhengfeng, et al. A lightweight configurable XOR RO-PUF design based on xilinx FPGA[C]. Proceedings of 2021 IEEE 4th International Conference on Electronics Technology (ICET), Chengdu, China, 2021: 83–88.
    [18]
    YAMAMOTO D, SAKIYAMA K, IWAMOTO M, et al. Variety enhancement of PUF responses using the locations of random outputting RS latches[J]. Journal of Cryptographic Engineering, 2013, 3(4): 197–211. doi: 10.1007/s13389-012-0044-0
    [19]
    CHALLA R P, ISLAM S A, and KATKOORI S. An SR flip-flop based physical unclonable functions for hardware security[C]. Proceedings of the 62nd International Midwest Symposium on Circuits and Systems (MWSCAS), Dallas, USA, 2019: 574–577.
    [20]
    WANG Jiadong, CUI Aijiao, LI Mengyang, et al. An ultra-low overhead LUT-based PUF for FPGA[C]. Proceedings of 2016 IEEE Asian Hardware-oriented Security and Trust, Yilan, China, 2016: 1–6.
    [21]
    孙子文, 叶乔. 利用震荡环频率特性提取多位可靠信息熵的物理不可克隆函数研究[J]. 电子与信息学报, 2021, 43(1): 234–241. doi: 10.11999/JEIT191013

    SUN Ziwen and YE Qiao. Study on the physical unclonable function of the reliable information entropy extracted by the frequency characteristic of oscillating ring[J]. Journal of Electronics &Information Technology, 2021, 43(1): 234–241. doi: 10.11999/JEIT191013
    [22]
    HATA H and ICHIKAWA S. FPGA implementation of metastability-based true random number generator[J]. IEICE Transactions on Information and Systems, 2012, E95.D(2): 426–436. doi: 10.1587/transinf.E95.D.426
    [23]
    XILINX Corporation. 7 series FPGAs configurable logic block user guide[EB/OL]. https://www.xilinx.com/content/dam/xilinx/support/documentation/user_guides/ug474_7Series_CLB.pdf, 2020.
    [24]
    GE Lulu and PARHI K K. Molecular MUX-based physical unclonable functions[C]. Proceedings of 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, 2020: 482–487.
    [25]
    RAMANUJAM S and BURLESON W. Reconfiguring the mux-based arbiter PUF using FeFETs[C]. Proceedings of the 22nd International Symposium on Quality Electronic Design (ISQED), Santa Clara, USA, 2021: 257–262.
    [26]
    RUKHIN A, SOTO J, NECHVATAL J, et al. A statistical test suite for random and pseudorandom number generators for cryptographic applications[R]. NIST Special Publication 800-220, 2001.
    [27]
    CUI Yijun, GU Chongyan, MA Qingqing, et al. Lightweight modeling attack-resistant multiplexer-based multi-PUF (MMPUF) design on FPGA[J]. Electronics, 2020, 9(5): 815. doi: 10.3390/electronics9050815
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