A Universal Test Access Port Controller Circuit Design for Chiplet Testing

CAI Zhikuang; ZHOU Guopeng; SONG Jian; WANG Zixuan; GUO Yufeng

doi:10.11999/JEIT220854

Volume 45 Issue 5

May 2023

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Article Navigation > Journal of Electronics & Information Technology > 2023 > 45(5): 1593-1601

CAI Zhikuang, ZHOU Guopeng, SONG Jian, WANG Zixuan, GUO Yufeng. A Universal Test Access Port Controller Circuit Design for Chiplet Testing[J]. Journal of Electronics & Information Technology, 2023, 45(5): 1593-1601. doi: 10.11999/JEIT220854

Citation:

CAI Zhikuang, ZHOU Guopeng, SONG Jian, WANG Zixuan, GUO Yufeng. A Universal Test Access Port Controller Circuit Design for Chiplet Testing[J]. Journal of Electronics & Information Technology, 2023, 45(5): 1593-1601. doi: 10.11999/JEIT220854

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A Universal Test Access Port Controller Circuit Design for Chiplet Testing

doi: 10.11999/JEIT220854

CAI Zhikuang^{1, 2},
ZHOU Guopeng¹,
SONG Jian¹,
WANG Zixuan^{1, 2
,
,},
GUO Yufeng^{1, 2}

1.
College of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210003, China
2.
National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology, Nanjing 210003, China

Funds: The National Natural Science Foundation of China (61974073)

Received Date: 2022-06-27
Rev Recd Date: 2022-07-26

Available Online: 2022-07-29

Publish Date: 2023-05-10

Abstract

Abstract

In the post-Moore era, Chiplet is the most hottest integration technique for heterogeneous integrated circuit, which is characterized by complex multi-core stacked structures. In order to solve the post-bonding test problem of Chiplet in different stacked structures, a Universal Test Access Port Controller (UTAPC) circuit is proposed based on IEEE 1838 standard protocol. Based on the traditional Test Access Port (TAP) controller, the Chiplet Dedicated Finite State Machine (CDFSM) is designed, also the Chiplet configuration registers and Chiplet test interface circuit are added. Under the influence of the configuration registers’ control signals generated by the CDFSM, the configuration signals outputted from the Chiplet configuration registers are used to control the Chiplet test interface circuit to set up the effective test path of Chiplet, which realized to access cores cross layers. The simulation results demonstrate that the proposed UTAPC circuit is suitable for the design for test of Chiplet with arbitrary stacked structures. It can not only choose to test cores flexibly, but also save the resources of test ports and test time, as well as improve the test efficiency.
- 3D integrated circuit,
- Chiplet,
- Interposer,
- Design for test,
- IEEE 1838 standard protocol

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References(15)

References

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