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Volume 45 Issue 1
Jan.  2023
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LIU Dongsheng, WEI Lai, ZOU Xuecheng, LU Jiahao, CHENG Xuan, HU Ang, LI Dejian, ZHAO Xu, JIANG Quming. Design of Hybrid Multimode Convolutional Neural Network Accelerator for Electrocardiogram Detection[J]. Journal of Electronics & Information Technology, 2023, 45(1): 33-41. doi: 10.11999/JEIT220534
Citation: LIU Dongsheng, WEI Lai, ZOU Xuecheng, LU Jiahao, CHENG Xuan, HU Ang, LI Dejian, ZHAO Xu, JIANG Quming. Design of Hybrid Multimode Convolutional Neural Network Accelerator for Electrocardiogram Detection[J]. Journal of Electronics & Information Technology, 2023, 45(1): 33-41. doi: 10.11999/JEIT220534

Design of Hybrid Multimode Convolutional Neural Network Accelerator for Electrocardiogram Detection

doi: 10.11999/JEIT220534
Funds:  The National Natural Science Foundation of China (62134002), The National Key Research and Development Program of China (2021YFA0715502), The Key Research and Development Project of Hubei Province (YFYB2020000413), The Introduced Innovative R&D Team Program of Dongguan (201760712600139)
  • Received Date: 2022-04-28
  • Rev Recd Date: 2022-06-18
  • Available Online: 2022-06-28
  • Publish Date: 2023-01-17
  • With the increasing scarcity of medical resources and the aging of the population, cardiovascular disease has posed a great threat to human health. Portable devices with ElectroCardioGram (ECG) detection can effectively reduce the threat of cardiovascular disease to patients. In this paper, a hybrid multi-mode Convolutional Neural Network(CNN) accelerator is designed for monitoring the patient's ECG. Firstly, a one-Dimensional Convolutional Neural Network(1D-CNN) model is introduced for ECG classification, then an efficient accelerator is designed for this model, which adopts a multi-parallel expansion strategy and multi-data stream operation mode to complete the acceleration and optimization of convolution loops. The proposed operation mode can highly reuse data in time and space, and improve the utilization of hardware resources, thereby improving the hardware efficiency of the hardware accelerator. Finally, the prototype verification is completed based on the Xilinx ZC706 hardware platform. The results show 2247 LUTs and 80 DSPs are consumed. At 200 MHz operating frequency, the overall performance can reach 28.1 GOPS, and the hardware efficiency reaches 12.82 GOPS/kLUT.
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