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Volume 45 Issue 5
May  2023
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YAO Maoqun, LIU Zhiqiang. Design of Quaternary Logic Current Mode CMOS Add-subtract Circuit Based on Comparator[J]. Journal of Electronics & Information Technology, 2023, 45(5): 1852-1858. doi: 10.11999/JEIT220360
Citation: YAO Maoqun, LIU Zhiqiang. Design of Quaternary Logic Current Mode CMOS Add-subtract Circuit Based on Comparator[J]. Journal of Electronics & Information Technology, 2023, 45(5): 1852-1858. doi: 10.11999/JEIT220360

Design of Quaternary Logic Current Mode CMOS Add-subtract Circuit Based on Comparator

doi: 10.11999/JEIT220360
Funds:  The National Natural Science Foundation of China (61771179)
  • Received Date: 2022-03-31
  • Rev Recd Date: 2022-06-14
  • Available Online: 2022-06-20
  • Publish Date: 2023-05-10
  • A multiple valued current mode comparator is introduced to control the threshold of current mode CMOS circuits. Compared with binary logic circuits, a single wire of multiple valued logic circuits allows more information transmission. Compared with voltage signal, current signal is easy to realize arithmetic operations, such as addition and subtraction, which is more convenient in the design of multiple valued logic. At the same time, the design method of quaternary valued basic unit based on comparator is proposed, and the designs of quaternary valued max, min and inverter are realized. On this basis, full adder and subtractor are designed and realized. The design method is also applicable to binary, ternary and n-valued logic. The experimental results show that the designed circuit has correct logic function, lower power consumption and fewer transistors than the current mode CMOS full adder in the relevant literature.
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