Convolutional Neural Network Accelerator Architecture Design for Ultimate Edge Computing Scenario

WU Ruidong; LIU Bing; FU Ping; JI Xinglong; LU Wenshuai

doi:10.11999/JEIT220130

Volume 45 Issue 6

Jun. 2023

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Article Navigation > Journal of Electronics & Information Technology > 2023 > 45(6): 1933-1943

WU Ruidong, LIU Bing, FU Ping, JI Xinglong, LU Wenshuai. Convolutional Neural Network Accelerator Architecture Design for Ultimate Edge Computing Scenario[J]. Journal of Electronics & Information Technology, 2023, 45(6): 1933-1943. doi: 10.11999/JEIT220130

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WU Ruidong, LIU Bing, FU Ping, JI Xinglong, LU Wenshuai. Convolutional Neural Network Accelerator Architecture Design for Ultimate Edge Computing Scenario[J]. Journal of Electronics & Information Technology, 2023, 45(6): 1933-1943. doi: 10.11999/JEIT220130

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Convolutional Neural Network Accelerator Architecture Design for Ultimate Edge Computing Scenario

doi: 10.11999/JEIT220130

1.
School of Electronics and Information Engineering, Harbin Institute of Technology, Harbin 150000, China
2.
Qiyuan Laboratory, Beijing 100089, China

Funds: The National Natural Science Foundation of China (62171156)

Received Date: 2022-02-15
Rev Recd Date: 2022-07-10

Available Online: 2022-07-15

Publish Date: 2023-06-10

Abstract

Abstract

In order to meet the requirements of performance and power in Ultimate Edge Computing (UEC) scenario, a Convolutional Neural Network (CNN) accelerator architecture is proposed with 16 Bit quantization model that does not rely on external memory. The basic structure of proposed architecture is Field Programmable Gate Array (FPGA) with multi-core CNN full pipeline accelerator. On this basis, the optimization of intra-layer mapping and inter-layer fusion of accelerator is realized. Then, the evaluation of computing resource and memory resource are theoretically completed by building the corresponding model. Under the guidance of this model, the resource utilization and computing efficiency are maximized through design space exploration, and the peak computing power of accelerator is fully exploited with limited resource constraint. Finally, taking fast human detection of nano Unmanned Aerial Vehicle (UAV) as an example, the verification and analysis of architecture are completed through experiments. Experimental results show that in the inference of human body detection neural network based on Single Shot multibox Detector (SSD), the performance is achieved with the speed of frame rate 137 and 34 at 100 MHz and 25 MHz, and the corresponding power is 0.514 W and 0.263 W, respectively, which meets the performance and power requirements of real-time image processing in typical UEC scenarios such as autonomous computing of nano-UAV.
- Ultimate Edge Computing(UEC),
- Convolutional Neural Network(CNN),
- Field Programmable Gate Array (FPGA),
- Accelerator architecture

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References(24)

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