Citation: | QU Tongzhou, DAI Zibin, CHEN Lin, LIU Yanjiang. A Hybrid Granularity Parallel Arithmetical Unit for Stream Cipher[J]. Journal of Electronics & Information Technology, 2023, 45(1): 78-86. doi: 10.11999/JEIT211579 |
[1] |
KOTESHWARA S, KUMAR M, and PATTNAIK P. Performance optimization of lattice post-quantum cryptographic algorithms on many-core processors[C]. 2020 IEEE International Symposium on Performance Analysis of Systems and Software, Boston, USA, 2020: 223–225.
|
[2] |
JIAO Lin, HAO Yonglin, and FENG Dengguo. Stream cipher designs: A review[J]. Science China Information Sciences, 2020, 63(3): 131101. doi: 10.1007/s11432-018-9929-x
|
[3] |
DAI Zibin, LI Wei, CHEN Tao, et al. Design and implementation of a high-speed reconfigurable feedback shift register[C]. 2008 4th IEEE International Conference on Circuits and Systems for Communications, Shanghai, China, 2008: 338–342.
|
[4] |
徐光明, 徐金甫, 常忠祥, 等. 序列密码非线性反馈移存器的可重构研究[J]. 计算机应用研究, 2015, 32(9): 2823–2826. doi: 10.3969/j.issn.1001-3695.2015.09.062
XU Guangming, XU Jinfu, CHANG Zhongxiang, et al. Reconfigurability study on nonlinear feedback shift registers in stream cipher[J]. Application Research of Computers, 2015, 32(9): 2823–2826. doi: 10.3969/j.issn.1001-3695.2015.09.062
|
[5] |
NAN Longmei, ZENG Xiaoyang, WANG Zhouchuang, et al. Research of a reconfigurable coarse-grained cryptographic processing unit based on different operation similar structure[C]. The 2017 IEEE 12th International Conference on ASIC, Guiyang, China, 2017: 191–194.
|
[6] |
NAN Longmei, YANG Xuan, ZENG Xiaoyang, et al. A VLIW architecture stream cryptographic processor for information security[J]. China Communications, 2019, 16(6): 185–199. doi: 10.23919/JCC.2019.06.015
|
[7] |
管子铭. 序列密码可重构处理结构研究与设计[D]. [硕士论文], 解放军信息工程大学, 2009.
GUAN Ziming. Research and design of sequence cipher reconfigurable processing architecture[D]. [Master dissertation], PLA Information Engineering University, 2009.
|
[8] |
DU Yiran, LI Wei, DAI Zibin, et al. PVHArray: An energy-efficient reconfigurable cryptographic logic array with intelligent mapping[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020, 28(5): 1302–1315. doi: 10.1109/TVLSI.2020.2972392
|
[9] |
LIU Leibo, WANG Bo, DENG Chenchen, et al. Anole: A highly efficient dynamically reconfigurable crypto-processor for symmetric-key algorithms[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37(12): 3081–3094. doi: 10.1109/TCAD.2018.2801229
|
[10] |
SAYILAR G and CHIOU D. Cryptoraptor: High throughput reconfigurable cryptographic processor[C]. 2014 IEEE/ACM International Conference on Computer-Aided Design, San Jose; USA, 2014: 155–161.
|
[11] |
IBRAHIM M I, KHAN M I W, JUVEKAR C S, et al. 29.8 THzID: A 1.6mm2 package-less cryptographic identification tag with backscattering and beam-steering at 260GHz[C]. 2020 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, USA, 2020: 454–456.
|
[12] |
杨锦江. 基于可重构计算的密码处理器关键技术研究[D]. [博士论文], 东南大学, 2018.
YANG Jinjiang. Research on key technologies of reconfigurable cryptographic processors[D]. [Ph. D. dissertation], Southeast University, 2018.
|
[13] |
XUE Yuqian and DAI Zibin. Reconfiurable multi-launch pipeline processing architecture for block cipher[J]. Application of Electronic Technique, 2020, 46(4): 40–44,48. doi: 10.16157/j.issn.0258-7998.200005
|
[14] |
KITSOS P, SKLAVOS N, PROVELENGIOS G, et al. FPGA-based performance analysis of stream ciphers ZUC, Snow3g, grain V1, mickey V2, trivium and E0[J]. Microprocessors and Microsystems, 2013, 37(2): 235–245. doi: 10.1016/j.micpro.2012.09.007
|
[15] |
STILLMAKER A and BAAS B. Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm[J]. Integration, 2017, 58: 74–81. doi: 10.1016/j.vlsi.2017.02.002
|