Design of High Precision Low Power Approximate Floating-point Multiplier Based on Partial Product Probability Analysis

YAN Chenggang; ZHAO Xuan; XU Chenyu; CHEN Ke; GE Jipeng; WANG Chenghua; LIU Weiqiang

doi:10.11999/JEIT211485

Volume 45 Issue 1

Jan. 2023

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Article Navigation > Journal of Electronics & Information Technology > 2023 > 45(1): 87-95

YAN Chenggang, ZHAO Xuan, XU Chenyu, CHEN Ke, GE Jipeng, WANG Chenghua, LIU Weiqiang. Design of High Precision Low Power Approximate Floating-point Multiplier Based on Partial Product Probability Analysis[J]. Journal of Electronics & Information Technology, 2023, 45(1): 87-95. doi: 10.11999/JEIT211485

Citation:

YAN Chenggang, ZHAO Xuan, XU Chenyu, CHEN Ke, GE Jipeng, WANG Chenghua, LIU Weiqiang. Design of High Precision Low Power Approximate Floating-point Multiplier Based on Partial Product Probability Analysis[J]. Journal of Electronics & Information Technology, 2023, 45(1): 87-95. doi: 10.11999/JEIT211485

Citation:

YAN Chenggang, ZHAO Xuan, XU Chenyu, CHEN Ke, GE Jipeng, WANG Chenghua, LIU Weiqiang. Design of High Precision Low Power Approximate Floating-point Multiplier Based on Partial Product Probability Analysis[J]. Journal of Electronics & Information Technology, 2023, 45(1): 87-95. doi: 10.11999/JEIT211485

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Design of High Precision Low Power Approximate Floating-point Multiplier Based on Partial Product Probability Analysis

doi: 10.11999/JEIT211485

College of Electronic and Information Engineering/College of Integrated Circuits, Nanjing University of Aeronautics and Astronautics, Nanjing 211106, China

Funds: The National Natural Science Foundation of China (62101246, 62022041, 62101252), The Natural Science Foundation of Jiangsu Province (BK20200417), The Innovative and Entrepreneurial Talents of Jiangsu Province (2020-30377)

Received Date: 2021-12-10
Accepted Date: 2022-03-03
Rev Recd Date: 2022-02-24

Available Online: 2022-03-08

Publish Date: 2023-01-17

Abstract

Abstract

Floating-point multipliers are the key operational units in High Dynamic Range(HDR) image processing and wireless communication systems. Compared to the fixed-point multipliers, floating-point multipliers have a higher dynamic range and also higher complexity. As a newly emerging paradigm, the hardware resources and power consumption of the circuits can be greatly reduced by approximate computing within an acceptable accuracy loss. According to the probability of 1 in the partial product array, an Approximate Floating-point Multiplier(App-Fp-Mul) is proposed in this paper. An approximate 4-2 compressor and or-gate based compression method are proposed to reduce the resource and power consumption of the floating-point multiplier with small precision loss. Compared with the accurate design, the proposed approximate floating-point multiplier can reduce the area, and power delay product by 20%, and 58% respectively when the Normalized Mean Error Distance (NMED) is 0.0014. And the proposed floating-point multiplier has higher accuracy and a smaller power delay product than the existing approximate designs with the same approximate bit width. Finally, the proposed approximate floating-point multiplier is verified with high dynamic range image processing application. The result of processing can reach 83.16 dB peak signal to noise ratio and 99.9989% structure similarity, which is obviously better than the existing approximate design.
- Approximate computing,
- Approximate Floating-point Multiplier(App-Fp-Mul),
- Partial product probability analysis,
- Low power consumption

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References(24)

References

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